2021-01-16 15:45:10 +00:00
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/* SPDX-License-Identifier: MIT */
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2021-01-30 06:14:38 +00:00
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#include "exception.h"
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2021-01-30 08:02:35 +00:00
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#include "cpu_regs.h"
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2021-01-16 15:45:10 +00:00
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#include "uart.h"
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#include "utils.h"
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extern char _vectors_start[0];
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2021-01-30 06:14:38 +00:00
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volatile enum exc_guard_t exc_guard = GUARD_OFF;
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volatile int exc_count = 0;
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2021-01-30 07:03:45 +00:00
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static char *ec_table[] = {
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[0x00] = "unknown",
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[0x01] = "wf*",
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[0x03] = "c15 mcr/mrc",
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[0x04] = "c15 mcrr/mrrc",
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[0x05] = "c14 mcr/mrc",
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[0x06] = "ldc/stc",
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[0x07] = "FP off",
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[0x08] = "VMRS access",
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[0x09] = "PAC off",
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[0x0a] = "ld/st64b",
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[0x0c] = "c14 mrrc",
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[0x0d] = "branch target",
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[0x0e] = "illegal state",
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[0x11] = "svc in a32",
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[0x12] = "hvc in a32",
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[0x13] = "smc in a32",
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[0x15] = "svc in a64",
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[0x16] = "hvc in a64",
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[0x17] = "smc in a64",
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[0x18] = "other mcr/mrc/sys",
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[0x19] = "SVE off",
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[0x1a] = "eret",
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[0x1c] = "PAC failure",
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[0x20] = "instruction abort (lower)",
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[0x21] = "instruction abort (current)",
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[0x22] = "pc misaligned",
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[0x24] = "data abort (lower)",
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[0x25] = "data abort (current)",
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[0x26] = "sp misaligned",
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[0x28] = "FP exception (a32)",
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[0x2c] = "FP exception (a64)",
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[0x2f] = "SError",
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[0x30] = "BP (lower)",
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[0x31] = "BP (current)",
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[0x32] = "step (lower)",
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[0x33] = "step (current)",
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[0x34] = "watchpoint (lower)",
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[0x35] = "watchpoint (current)",
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[0x38] = "bkpt (a32)",
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[0x3a] = "vector catch (a32)",
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[0x3c] = "brk (a64)",
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};
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2021-01-16 15:45:10 +00:00
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void exception_initialize(void)
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{
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2021-01-30 08:02:51 +00:00
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msr(VBAR_EL2, _vectors_start);
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msr(DAIF, 0 << 6); // Enable SError, IRQ and FIQ
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}
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void exception_shutdown(void)
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{
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msr(DAIF, 7 << 6); // Disable SError, IRQ and FIQ
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2021-01-16 15:45:10 +00:00
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}
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void print_regs(u64 *regs)
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{
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2021-01-17 16:57:16 +00:00
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u64 sp = ((u64)(regs)) + 256;
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2021-01-16 15:45:10 +00:00
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printf("Running in EL%d\n", mrs(CurrentEL) >> 2);
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2021-01-30 10:25:14 +00:00
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printf("MPIDR: 0x%lx\n", mrs(MPIDR_EL1));
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2021-01-16 15:45:10 +00:00
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printf("Registers: (@%p)\n", regs);
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2021-01-28 06:27:35 +00:00
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printf(" x0-x3: %016lx %016lx %016lx %016lx\n", regs[0], regs[1], regs[2], regs[3]);
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printf(" x4-x7: %016lx %016lx %016lx %016lx\n", regs[4], regs[5], regs[6], regs[7]);
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printf(" x8-x11: %016lx %016lx %016lx %016lx\n", regs[8], regs[9], regs[10], regs[11]);
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printf("x12-x15: %016lx %016lx %016lx %016lx\n", regs[12], regs[13], regs[14], regs[15]);
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printf("x16-x19: %016lx %016lx %016lx %016lx\n", regs[16], regs[17], regs[18], regs[19]);
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printf("x20-x23: %016lx %016lx %016lx %016lx\n", regs[20], regs[21], regs[22], regs[23]);
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printf("x24-x27: %016lx %016lx %016lx %016lx\n", regs[24], regs[25], regs[26], regs[27]);
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2021-01-16 15:45:10 +00:00
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printf("x28-x30: %016lx %016lx %016lx\n", regs[28], regs[29], regs[30]);
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u64 elr = mrs(elr_el2);
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printf("PC: 0x%lx (rel: 0x%lx)\n", elr, elr - (u64)_base);
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2021-01-30 06:14:38 +00:00
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printf("SPSEL: 0x%lx\n", mrs(SPSEL));
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2021-01-16 15:45:10 +00:00
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printf("SP: 0x%lx\n", sp);
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2021-01-30 10:25:14 +00:00
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printf("SPSR_EL2: 0x%lx\n", mrs(SPSR_EL2));
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printf("FAR_EL2: 0x%lx\n", mrs(FAR_EL2));
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2021-01-30 07:03:45 +00:00
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const char *ec_desc = ec_table[(mrs(ESR_EL2) >> 26) & 0x3f];
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2021-01-30 10:25:14 +00:00
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printf("ESR_EL2: 0x%lx (%s)\n", mrs(ESR_EL2), ec_desc ? ec_desc : "unknown");
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2021-01-30 06:14:38 +00:00
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2021-01-30 07:23:18 +00:00
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u64 l2c_err_sts = mrs(SYS_L2C_ERR_STS);
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printf("L2C_ERR_STS: 0x%lx\n", l2c_err_sts);
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2021-01-30 06:14:38 +00:00
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printf("L2C_ERR_ADR: 0x%lx\n", mrs(SYS_L2C_ERR_ADR));
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printf("L2C_ERR_INF: 0x%lx\n", mrs(SYS_L2C_ERR_INF));
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2021-01-30 07:23:18 +00:00
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msr(SYS_L2C_ERR_STS, l2c_err_sts); // Clear the flag bits
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2021-01-30 06:14:38 +00:00
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if (is_ecore()) {
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printf("SYS_E_LSU_ERR_STS: 0x%lx\n", mrs(SYS_E_LSU_ERR_STS));
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printf("SYS_E_FED_ERR_STS: 0x%lx\n", mrs(SYS_E_FED_ERR_STS));
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printf("SYS_E_MMU_ERR_STS: 0x%lx\n", mrs(SYS_E_MMU_ERR_STS));
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} else {
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printf("SYS_LSU_ERR_STS: 0x%lx\n", mrs(SYS_LSU_ERR_STS));
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printf("SYS_FED_ERR_STS: 0x%lx\n", mrs(SYS_FED_ERR_STS));
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printf("SYS_MMU_ERR_STS: 0x%lx\n", mrs(SYS_MMU_ERR_STS));
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}
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2021-01-16 15:45:10 +00:00
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}
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void exc_sync(u64 *regs)
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{
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2021-01-30 06:14:38 +00:00
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u64 elr;
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u32 insn;
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2021-01-16 15:45:10 +00:00
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uart_puts("Exception: SYNC");
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2021-01-30 08:01:07 +00:00
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sysop("isb");
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sysop("dsb sy");
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2021-01-16 15:45:10 +00:00
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print_regs(regs);
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2021-01-30 06:14:38 +00:00
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switch (exc_guard) {
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case GUARD_SKIP:
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elr = mrs(ELR_EL2) + 4;
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break;
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case GUARD_MARK:
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// Assuming this is a load or store, dest reg is in low bits
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insn = read32(mrs(ELR_EL2));
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regs[insn & 0x1f] = 0xacce5515abad1dea;
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elr = mrs(ELR_EL2) + 4;
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break;
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case GUARD_RETURN:
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regs[0] = 0xacce5515abad1dea;
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elr = regs[30];
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exc_guard = GUARD_OFF;
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break;
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case GUARD_OFF:
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default:
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reboot();
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}
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exc_count++;
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printf("Recovering from exception (ELR=0x%lx)\n", elr);
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msr(ELR_EL2, elr);
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2021-01-30 08:01:07 +00:00
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sysop("isb");
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sysop("dsb sy");
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2021-01-16 15:45:10 +00:00
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}
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void exc_irq(u64 *regs)
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{
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2021-01-23 13:32:35 +00:00
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#ifdef DEBUG_UART_IRQS
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u32 ucon, utrstat, uerstat, ufstat;
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ucon = read32(0x235200004);
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utrstat = read32(0x235200010);
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uerstat = read32(0x235200014);
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ufstat = read32(0x235200018);
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#endif
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2021-01-16 15:45:10 +00:00
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uart_puts("Exception: IRQ");
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u32 reason = read32(0x23b102004);
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2021-02-03 10:18:34 +00:00
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printf(" type: %d num: %d mpidr: %x\n", reason >> 16, reason & 0xffff, mrs(MPIDR_EL1));
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2021-01-16 15:45:10 +00:00
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2021-01-23 13:32:35 +00:00
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#ifdef DEBUG_UART_IRQS
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printf(" UCON: 0x%x\n", ucon);
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printf(" UTRSTAT: 0x%x\n", utrstat);
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printf(" UERSTAT: 0x%x\n", uerstat);
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printf(" UFSTAT: 0x%x\n", ufstat);
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#endif
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2021-01-16 20:57:43 +00:00
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UNUSED(regs);
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2021-01-16 15:45:10 +00:00
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// print_regs(regs);
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}
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void exc_fiq(u64 *regs)
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{
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uart_puts("Exception: FIQ");
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u32 timer_ctl = mrs(CNTP_CTL_EL0);
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2021-02-06 06:09:22 +00:00
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if (timer_ctl == 0x5) {
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uart_puts(" PHYS timer IRQ, masking");
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msr(CNTP_CTL_EL0, 7L);
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}
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2021-01-16 15:45:10 +00:00
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2021-02-06 06:09:22 +00:00
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timer_ctl = mrs(CNTV_CTL_EL0);
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2021-01-16 15:45:10 +00:00
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if (timer_ctl == 0x5) {
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2021-02-06 06:09:22 +00:00
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uart_puts(" VIRT timer IRQ, masking");
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2021-01-16 19:44:44 +00:00
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msr(CNTP_CTL_EL0, 7L);
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2021-01-16 15:45:10 +00:00
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}
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2021-02-06 06:09:22 +00:00
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timer_ctl = mrs(CNTP_CTL_EL02);
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if (timer_ctl == 0x5) {
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uart_puts(" PHYS EL02 timer IRQ, masking");
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msr(CNTP_CTL_EL02, 7L);
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}
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timer_ctl = mrs(CNTV_CTL_EL02);
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if (timer_ctl == 0x5) {
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uart_puts(" VIRT EL02 timer IRQ, masking");
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msr(CNTP_CTL_EL02, 7L);
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}
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2021-01-16 20:57:43 +00:00
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UNUSED(regs);
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2021-01-16 15:45:10 +00:00
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// print_regs(regs);
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}
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void exc_serr(u64 *regs)
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{
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printf("Exception: SError\n");
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2021-01-30 08:01:07 +00:00
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sysop("isb");
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sysop("dsb sy");
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2021-01-16 15:45:10 +00:00
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print_regs(regs);
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2021-01-30 09:48:00 +00:00
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// reboot();
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2021-01-16 15:45:10 +00:00
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}
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