mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-10 01:34:12 +00:00
Basic exceptions, irq, cache mgmt support
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
73e79c5372
commit
81aaf2ed35
17 changed files with 447 additions and 57 deletions
9
Makefile
9
Makefile
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@ -8,8 +8,9 @@ LDFLAGS := -T m1n1.ld -EL -maarch64elf --no-undefined -X -shared -Bsymbolic \
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-z notext --no-apply-dynamic-relocs --orphan-handling=warn --strip-debug \
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-z nocopyreloc --gc-sections -pie
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OBJECTS := adt.o bootlogo_128.o bootlogo_256.o fb.o main.o proxy.o start.o startup.o \
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string.o uart.o uartproxy.o utils.o utils_asm.o vsprintf.o
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OBJECTS := adt.o bootlogo_128.o bootlogo_256.o exception.o exception_asm.o fb.o \
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main.o memory.o proxy.o start.o startup.o string.o uart.o uartproxy.o utils.o \
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utils_asm.o vsprintf.o
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BUILD_OBJS := $(patsubst %,build/%,$(OBJECTS))
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NAME := m1n1
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@ -42,14 +43,14 @@ build/%.o: src/%.c
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build/$(NAME).elf: $(BUILD_OBJS) m1n1.ld
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@echo " LD $@"
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@$(LD) $(LDFLAGS) -o $@ $(BUILD_OBJS)
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build/$(NAME).macho: build/$(NAME).elf
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@echo " MACHO $@"
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@$(OBJCOPY) -O binary $< $@
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build/build_tag.h:
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@echo " TAG $@"
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@echo "#define BUILD_TAG \"$$(git describe --always --dirty)\"" > $@
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@echo "#define BUILD_TAG \"$$(git describe --always --dirty)\"" > $@
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build/%.bin: data/%.png
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@echo " IMG $@"
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10
m1n1.ld
10
m1n1.ld
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@ -30,7 +30,7 @@ SECTIONS {
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LONG(_cmd_end - _cmd_start); /* sizeofcmds */
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LONG(4); /* flags */
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LONG(0); /* reserved */
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_cmd_start = .;
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/* unix_thread (entrypoint) */
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@ -41,7 +41,7 @@ SECTIONS {
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. += 32 * 8; /* useless registers */
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QUAD(_start + _va_off) /* pc */
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. += 8; /* useless registers */
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ASSERT(. - _cmd_start == 0x120, "Bad unix_thread structure");
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/* segment: mach-o structures */
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@ -57,7 +57,7 @@ SECTIONS {
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LONG(PROT_READ); /* initprot */
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LONG(0); /* nsects */
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LONG(0); /* flags */
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/* segment: text */
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LONG(0x19); /* type = SEGMENT_64 */
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LONG(0x48); /* cmdsize */
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@ -101,7 +101,7 @@ SECTIONS {
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LONG(0); /* flags */
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_cmd_end = .;
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. = ALIGN(0x4000);
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_hdr_end = .;
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} :hdr
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@ -171,7 +171,7 @@ SECTIONS {
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*(.data.rel.ro)
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}
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ASSERT(SIZEOF(.empty) == 0, "Unexpected sections detected!")
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.got.plt (NOLOAD) : {
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*(.got.plt)
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}
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@ -25,7 +25,7 @@ print("Loading %d bytes to 0x%x" % (len(payload), new_base))
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iface.writemem(new_base + 0x4000, payload[0x4000:], True)
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entry = new_base + 0x4000
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entry = new_base + 0x4800
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print("Jumping to 0x%x" % entry)
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@ -259,10 +259,17 @@ class M1N1Proxy:
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P_MEMSET16 = 0x206
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P_MEMSET8 = 0x207
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P_DC_FLUSHRANGE = 0x300
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P_DC_INVALRANGE = 0x301
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P_DC_FLUSHALL = 0x302
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P_IC_INVALALL = 0x303
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P_IC_IALLUIS = 0x300
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P_IC_IALLU = 0x301
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P_IC_IVAU = 0x302
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P_DC_IVAC = 0x303
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P_DC_ISW = 0x304
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P_DC_CSW = 0x305
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P_DC_CISW = 0x306
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P_DC_ZVA = 0x307
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P_DC_CVAC = 0x308
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P_DC_CVAU = 0x309
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P_DC_CIVAC = 0x30a
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def __init__(self, iface, debug=False):
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self.debug = debug
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@ -417,15 +424,29 @@ class M1N1Proxy:
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self.request(self.P_MEMSET16, dst, src, size)
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def memset8(self, dst, src, size):
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self.request(self.P_MEMSET8, dst, src, size)
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def dc_flushrange(self, addr, size):
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self.request(self.P_DC_FLUSHRANGE, addr, size)
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def dc_invalrange(self, addr, size):
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self.request(self.P_DC_INVALRANGE, addr, size)
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def dc_flushall(self):
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self.request(self.P_DC_FLUSHALL)
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def ic_invalall(self):
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self.request(self.P_IC_INVALALL)
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def ic_ialluis(self):
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self.request(self.P_IC_IALLUIS)
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def ic_iallu(self):
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self.request(self.P_IC_IALLU)
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def ic_ivau(self, addr, size):
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self.request(self.P_IC_IVAU, addr, size)
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def ic_ivac(self, addr, size):
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self.request(self.P_IC_IVAC, addr, size)
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def dc_isw(self, sw):
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self.request(self.P_DC_ISW, sw)
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def dc_csw(self, sw):
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self.request(self.P_DC_CSW, sw)
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def dc_cisw(self, sw):
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self.request(self.P_DC_CISW, sw)
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def dc_zva(self, addr, size):
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self.request(self.P_DC_ZVA, addr, size)
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def dc_cvac(self, addr, size):
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self.request(self.P_DC_CVAC, addr, size)
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def dc_cvau(self, addr, size):
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self.request(self.P_DC_CVAU, addr, size)
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def dc_civac(self, addr, size):
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self.request(self.P_DC_CIVAC, addr, size)
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if __name__ == "__main__":
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import serial
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84
src/exception.c
Normal file
84
src/exception.c
Normal file
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@ -0,0 +1,84 @@
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/* SPDX-License-Identifier: MIT */
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#include "uart.h"
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#include "utils.h"
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extern char _vectors_start[0];
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void exception_initialize(void)
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{
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printf("Initializing exceptions...\n");
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msr(vbar_el2, _vectors_start);
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}
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void print_regs(u64 *regs)
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{
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u64 sp = ((u64)(regs)) - (8 * 31);
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printf("Running in EL%d\n", mrs(CurrentEL) >> 2);
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printf("Registers: (@%p)\n", regs);
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printf(" x0-x3: %016lx %016lx %016lx %016lx\n", regs[0], regs[1], regs[2],
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regs[3]);
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printf(" x4-x7: %016lx %016lx %016lx %016lx\n", regs[4], regs[5], regs[6],
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regs[7]);
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printf(" x8-x11: %016lx %016lx %016lx %016lx\n", regs[8], regs[9], regs[10],
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regs[11]);
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printf("x12-x15: %016lx %016lx %016lx %016lx\n", regs[12], regs[13],
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regs[14], regs[15]);
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printf("x16-x19: %016lx %016lx %016lx %016lx\n", regs[16], regs[17],
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regs[18], regs[19]);
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printf("x20-x23: %016lx %016lx %016lx %016lx\n", regs[20], regs[21],
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regs[22], regs[23]);
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printf("x24-x27: %016lx %016lx %016lx %016lx\n", regs[24], regs[25],
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regs[26], regs[27]);
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printf("x28-x30: %016lx %016lx %016lx\n", regs[28], regs[29], regs[30]);
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u64 elr = mrs(elr_el2);
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printf("PC: 0x%lx (rel: 0x%lx)\n", elr, elr - (u64)_base);
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printf("SPSEL: 0x%lx\n", mrs(spsel));
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printf("SP: 0x%lx\n", sp);
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printf("SPSR_EL2: 0x%x\n", mrs(spsr_el2));
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}
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void exc_sync(u64 *regs)
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{
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uart_puts("Exception: SYNC");
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print_regs(regs);
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reboot();
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}
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void exc_irq(u64 *regs)
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{
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uart_puts("Exception: IRQ");
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u32 reason = read32(0x23b102004);
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printf(" type: %d num: %d\n", reason >> 16, reason & 0xffff);
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// print_regs(regs);
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}
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void exc_fiq(u64 *regs)
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{
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uart_puts("Exception: FIQ");
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u32 timer_ctl = mrs(CNTP_CTL_EL0);
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if (timer_ctl == 0x5) {
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uart_puts(" timer IRQ, masking");
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msr(CNTP_CTL_EL0, 7);
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}
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// print_regs(regs);
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}
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void exc_serr(u64 *regs)
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{
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printf("Exception: SError\n");
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print_regs(regs);
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reboot();
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}
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8
src/exception.h
Normal file
8
src/exception.h
Normal file
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: MIT */
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#ifndef __EXCEPTION_H__
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#define __EXCEPTION_H__
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void exception_initialize(void);
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#endif
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84
src/exception_asm.S
Normal file
84
src/exception_asm.S
Normal file
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@ -0,0 +1,84 @@
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/* spDx-License-Identifier: MIT */
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.globl exc_sync
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.globl exc_irq
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.globl exc_fiq
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.globl exc_serr
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.globl _vectors_start
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.globl _v_sp0_sync
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.type _v_sp0_sync, @function
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_v_sp0_sync:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl exc_sync
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b _exc_return
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.globl _v_sp0_irq
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.type _v_sp0_irq, @function
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_v_sp0_irq:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl exc_irq
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b _exc_return
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.globl _v_sp0_fiq
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.type _v_sp0_fiq, @function
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_v_sp0_fiq:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl exc_fiq
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b _exc_return
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.globl _v_sp0_serr
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.type _v_sp0_serr, @function
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_v_sp0_serr:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl exc_serr
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b _exc_return
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.globl push_hi_regs
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.type push_hi_regs, @function
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push_hi_regs:
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_exc_entry:
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stp x28, x29, [sp, #-16]!
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stp x26, x27, [sp, #-16]!
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stp x24, x25, [sp, #-16]!
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stp x22, x23, [sp, #-16]!
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stp x20, x21, [sp, #-16]!
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stp x18, x19, [sp, #-16]!
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stp x16, x17, [sp, #-16]!
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stp x14, x15, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x4, x5, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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mov x0, sp
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ret
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.globl _exc_return
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.type _exc_return, @function
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_exc_return:
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ldp x0, x1, [sp], #16
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ldp x2, x3, [sp], #16
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ldp x4, x5, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x14, x15, [sp], #16
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add sp, sp, #112
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ldr x30, [sp], #16
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eret
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15
src/main.c
15
src/main.c
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@ -10,7 +10,7 @@
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#include "../build/build_tag.h"
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//#define LOGO
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// #define LOGO
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void print_info(void)
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{
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@ -65,7 +65,9 @@ void m1n1_main(void)
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{
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printf("\n\nm1n1 v%s\n", BUILD_TAG);
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printf("Copyright (C) 2021 The Asahi Linux Contributors\n");
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printf("Licensed under the MIT license\n");
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printf("Licensed under the MIT license\n\n");
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printf("Running in EL%d\n\n", mrs(CurrentEL) >> 2);
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#ifdef LOGO
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fb_init();
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@ -75,15 +77,6 @@ void m1n1_main(void)
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print_info();
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disable_wdt();
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/*
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u64 dtaddr = ((u64)cur_boot_args.devtree) - cur_boot_args.virt_base +
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cur_boot_args.phys_base;*/
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// hexdump((void *)dtaddr, cur_boot_args.devtree_size);
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//
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// while (1)
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// uart_putbyte(uart_getbyte());
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printf("Running proxy...\n");
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uartproxy_run();
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|
|
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24
src/memory.c
Normal file
24
src/memory.c
Normal file
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|
@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: MIT */
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#include "memory.h"
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#include "utils.h"
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#define CACHE_LINE_SIZE 64
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#define CACHE_RANGE_OP(func, op) \
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void func(void *addr, size_t length) \
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{ \
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u64 p = (u64)addr; \
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u64 end = p + length; \
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while (p < end) { \
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cacheop(op, p); \
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p += CACHE_LINE_SIZE; \
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} \
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}
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CACHE_RANGE_OP(ic_ivau_range, "ic ivau")
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CACHE_RANGE_OP(dc_ivac_range, "dc ivac")
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CACHE_RANGE_OP(dc_zva_range, "dc zva")
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CACHE_RANGE_OP(dc_cvac_range, "dc cvac")
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CACHE_RANGE_OP(dc_cvau_range, "dc cvau")
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CACHE_RANGE_OP(dc_civac_range, "dc civac")
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15
src/memory.h
Normal file
15
src/memory.h
Normal file
|
|
@ -0,0 +1,15 @@
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|||
/* SPDX-License-Identifier: MIT */
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||||
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#ifndef MEMORY_H
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#define MEMORY_H
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#include "types.h"
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void ic_ivau_range(void *addr, size_t length);
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void dc_ivac_range(void *addr, size_t length);
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void dc_zva_range(void *addr, size_t length);
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void dc_cvac_range(void *addr, size_t length);
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void dc_cvau_range(void *addr, size_t length);
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void dc_civac_range(void *addr, size_t length);
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#endif
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43
src/proxy.c
43
src/proxy.c
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|
@ -1,11 +1,10 @@
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#include "proxy.h"
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#include "memory.h"
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#include "types.h"
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#include "uart.h"
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#include "utils.h"
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#include "xnuboot.h"
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|
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extern char _base[0];
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|
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int proxy_process(ProxyRequest *request, ProxyReply *reply)
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{
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callfunc *f;
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|
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@ -145,13 +144,39 @@ int proxy_process(ProxyRequest *request, ProxyReply *reply)
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request->args[2]);
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break;
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|
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/*
|
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case P_DC_FLUSHRANGE: dc_flushrange((void*)request->args[0],
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request->args[1]); break; case P_DC_INVALRANGE:
|
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dc_invalidaterange((void*)request->args[0], request->args[1]);
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break; case P_DC_FLUSHALL: dc_flushall(); break; case
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P_IC_INVALALL: ic_invalidateall(); break;
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*/
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case P_IC_IALLUIS:
|
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ic_ialluis();
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break;
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case P_IC_IALLU:
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ic_iallu();
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break;
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case P_IC_IVAU:
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ic_ivau_range((void *)request->args[0], request->args[1]);
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||||
break;
|
||||
case P_DC_IVAC:
|
||||
dc_ivac_range((void *)request->args[0], request->args[1]);
|
||||
break;
|
||||
case P_DC_ISW:
|
||||
dc_isw((void *)request->args[0]);
|
||||
break;
|
||||
case P_DC_CSW:
|
||||
dc_csw((void *)request->args[0]);
|
||||
break;
|
||||
case P_DC_CISW:
|
||||
dc_cisw((void *)request->args[0]);
|
||||
break;
|
||||
case P_DC_ZVA:
|
||||
dc_zva_range((void *)request->args[0], request->args[1]);
|
||||
break;
|
||||
case P_DC_CVAC:
|
||||
dc_cvac_range((void *)request->args[0], request->args[1]);
|
||||
break;
|
||||
case P_DC_CVAU:
|
||||
dc_cvau_range((void *)request->args[0], request->args[1]);
|
||||
break;
|
||||
case P_DC_CIVAC:
|
||||
dc_civac_range((void *)request->args[0], request->args[1]);
|
||||
break;
|
||||
|
||||
default:
|
||||
reply->status = S_BADCMD;
|
||||
|
|
|
|||
15
src/proxy.h
15
src/proxy.h
|
|
@ -41,10 +41,17 @@ typedef enum {
|
|||
P_MEMSET16,
|
||||
P_MEMSET8,
|
||||
|
||||
P_DC_FLUSHRANGE = 0x300, // Cache and memory ops
|
||||
P_DC_INVALRANGE,
|
||||
P_DC_FLUSHALL,
|
||||
P_IC_INVALALL,
|
||||
P_IC_IALLUIS = 0x300, // Cache and memory ops
|
||||
P_IC_IALLU,
|
||||
P_IC_IVAU,
|
||||
P_DC_IVAC,
|
||||
P_DC_ISW,
|
||||
P_DC_CSW,
|
||||
P_DC_CISW,
|
||||
P_DC_ZVA,
|
||||
P_DC_CVAC,
|
||||
P_DC_CVAU,
|
||||
P_DC_CIVAC,
|
||||
|
||||
} ProxyOp;
|
||||
|
||||
|
|
|
|||
98
src/start.S
98
src/start.S
|
|
@ -4,11 +4,68 @@
|
|||
#define UTRSTAT 0x010
|
||||
#define UTXH 0x020
|
||||
|
||||
#define WDT_BASE 0x23d2b0000
|
||||
#define WDT_COUNT 0x10
|
||||
#define WDT_ALARM 0x14
|
||||
#define WDT_CTL 0x1c
|
||||
|
||||
.extern _start_c
|
||||
.extern _stack_bot
|
||||
.extern _v_sp0_sync
|
||||
.extern _v_sp0_irq
|
||||
.extern _v_sp0_fiq
|
||||
.extern _v_sp0_serr
|
||||
|
||||
.section .init, "ax"
|
||||
|
||||
.globl _vectors_start
|
||||
_vectors_start:
|
||||
|
||||
mov x9, '0'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, '1'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, '2'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, '3'
|
||||
b exc_unk
|
||||
.align 7
|
||||
b _v_sp0_sync
|
||||
.align 7
|
||||
b _v_sp0_irq
|
||||
.align 7
|
||||
b _v_sp0_fiq
|
||||
.align 7
|
||||
b _v_sp0_serr
|
||||
.align 7
|
||||
mov x9, 'a'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 'b'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 'c'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 'd'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 'p'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 'q'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 'r'
|
||||
b exc_unk
|
||||
.align 7
|
||||
mov x9, 's'
|
||||
b exc_unk
|
||||
.align 7
|
||||
|
||||
.globl _start
|
||||
.type _start, @function
|
||||
_start:
|
||||
|
|
@ -46,6 +103,33 @@ _start:
|
|||
bl _start_c
|
||||
b .
|
||||
|
||||
.globl exc_unk
|
||||
.type exc_unk, @function
|
||||
exc_unk:
|
||||
mov w0, '\r'
|
||||
bl debug_putc
|
||||
mov w0, '\n'
|
||||
bl debug_putc
|
||||
mov w0, '!'
|
||||
bl debug_putc
|
||||
mov w0, 'E'
|
||||
bl debug_putc
|
||||
mov w0, 'x'
|
||||
bl debug_putc
|
||||
mov w0, 'C'
|
||||
bl debug_putc
|
||||
mov w0, ':'
|
||||
bl debug_putc
|
||||
mov w0, w9
|
||||
bl debug_putc
|
||||
mov w0, '!'
|
||||
bl debug_putc
|
||||
mov w0, '\r'
|
||||
bl debug_putc
|
||||
mov w0, '\n'
|
||||
bl debug_putc
|
||||
b reboot
|
||||
|
||||
.globl debug_putc
|
||||
.type debug_putc, @function
|
||||
debug_putc:
|
||||
|
|
@ -58,4 +142,16 @@ debug_putc:
|
|||
str w0, [x1, UTXH]
|
||||
ret
|
||||
|
||||
.pool
|
||||
.globl reboot
|
||||
.type reboot, @function
|
||||
reboot:
|
||||
ldr x1, =WDT_BASE
|
||||
mov w0, #0x100000
|
||||
str w0, [x1, #WDT_ALARM]
|
||||
mov w0, #0
|
||||
str w0, [x1, #WDT_COUNT]
|
||||
mov w0, #4
|
||||
str w0, [x1, #WDT_CTL]
|
||||
b .
|
||||
|
||||
.pool
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
#include "exception.h"
|
||||
#include "string.h"
|
||||
#include "types.h"
|
||||
#include "uart.h"
|
||||
|
|
@ -79,5 +80,6 @@ void _start_c(void *boot_args, void *base)
|
|||
adt = (void *)(((u64)cur_boot_args.devtree) - cur_boot_args.virt_base +
|
||||
cur_boot_args.phys_base);
|
||||
|
||||
exception_initialize();
|
||||
m1n1_main();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@
|
|||
#ifndef UART_H
|
||||
#define UART_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
void uart_init(void);
|
||||
|
||||
void uart_putbyte(u8 c);
|
||||
|
|
|
|||
28
src/utils.h
28
src/utils.h
|
|
@ -193,6 +193,33 @@ static inline u8 mask8(u64 addr, u8 clear, u8 set)
|
|||
return data;
|
||||
}
|
||||
|
||||
#define mrs(reg) \
|
||||
({ \
|
||||
u64 val; \
|
||||
__asm__ volatile("mrs\t%0, " #reg : "=r"(val)); \
|
||||
val; \
|
||||
})
|
||||
|
||||
#define msr(reg, val) ({ __asm__ volatile("msr\t" #reg ", %0" : : "r"(val)); })
|
||||
|
||||
#define sysop(op) __asm__ volatile(op)
|
||||
|
||||
#define cacheop(op, val) ({ __asm__ volatile(op ", %0" : : "r"(val)); })
|
||||
|
||||
#define ic_ialluis() sysop("ic ialluis")
|
||||
#define ic_iallu() sysop("ic iallu")
|
||||
#define ic_iavau(p) cacheop("ic ivau", p)
|
||||
#define dc_ivac(p) cacheop("dc ivac", p)
|
||||
#define dc_isw(p) cacheop("dc isw", p)
|
||||
#define dc_csw(p) cacheop("dc csw", p)
|
||||
#define dc_cisw(p) cacheop("dc cisw", p)
|
||||
#define dc_zva(p) cacheop("dc zva", p)
|
||||
#define dc_cvac(p) cacheop("dc cvac", p)
|
||||
#define dc_cvau(p) cacheop("dc cvau", p)
|
||||
#define dc_civac(p) cacheop("dc civac", p)
|
||||
|
||||
extern char _base[0];
|
||||
|
||||
/*
|
||||
* These functions are guaranteed to copy by reading from src and writing to dst
|
||||
* in <n>-bit units If size is not aligned, the remaining bytes are not copied
|
||||
|
|
@ -211,5 +238,6 @@ void regdump(u64 addr, int len);
|
|||
int sprintf(char *str, const char *fmt, ...);
|
||||
int debug_printf(const char *fmt, ...);
|
||||
void udelay(u32 d);
|
||||
void reboot(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ memcpy64:
|
|||
str x3, [x0], #8
|
||||
subs x2, x2, #8
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memset64
|
||||
|
|
@ -22,7 +22,7 @@ memset64:
|
|||
1: str x1, [x0], #8
|
||||
subs x2, x2, #8
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memcpy32
|
||||
|
|
@ -30,11 +30,11 @@ memset64:
|
|||
memcpy32:
|
||||
ands x2, x2, #~3
|
||||
beq 2f
|
||||
1: ldr x3, [x1], #4
|
||||
1: ldr w3, [x1], #4
|
||||
str w3, [x0], #4
|
||||
subs x2, x2, #4
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memset32
|
||||
|
|
@ -45,7 +45,7 @@ memset32:
|
|||
1: str w1, [x0], #4
|
||||
subs x2, x2, #4
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memcpy16
|
||||
|
|
@ -57,7 +57,7 @@ memcpy16:
|
|||
strh w3, [x0], #2
|
||||
subs x2, x2, #2
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memset16
|
||||
|
|
@ -68,7 +68,7 @@ memset16:
|
|||
1: strh w1, [x0], #2
|
||||
subs x2, x2, #2
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memcpy8
|
||||
|
|
@ -80,7 +80,7 @@ memcpy8:
|
|||
strb w3, [x0], #1
|
||||
subs x2, x2, #1
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
||||
.globl memset8
|
||||
|
|
@ -91,5 +91,5 @@ memset8:
|
|||
1: strb w1, [x0], #1
|
||||
subs x2, x2, #1
|
||||
bne 1b
|
||||
2:
|
||||
2:
|
||||
ret
|
||||
|
|
|
|||
Loading…
Reference in a new issue