2021-05-01 10:05:21 +00:00
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/* SPDX-License-Identifier: MIT */
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#include "hv.h"
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#include "assert.h"
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#include "cpu_regs.h"
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2021-05-08 12:54:07 +00:00
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#include "utils.h"
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2021-05-01 10:05:21 +00:00
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2021-05-25 11:04:20 +00:00
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#define HV_TICK_RATE 1000
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2021-05-04 15:24:52 +00:00
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void hv_enter_guest(u64 x0, u64 x1, u64 x2, u64 x3, void *entry);
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2021-05-04 10:36:23 +00:00
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extern char _hv_vectors_start[0];
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2021-05-25 11:04:20 +00:00
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u64 hv_tick_interval;
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2021-05-01 10:05:21 +00:00
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void hv_init(void)
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{
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// Enable physical timer for EL1
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2021-05-04 10:23:35 +00:00
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msr(CNTHCTL_EL2, CNTHCTL_EL1PTEN | CNTHCTL_EL1PCTEN);
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2021-05-01 10:05:21 +00:00
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hv_pt_init();
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// Configure hypervisor defaults
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msr(HCR_EL2, HCR_API | // Allow PAuth instructions
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HCR_APK | // Allow PAuth key registers
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HCR_TEA | // Trap external aborts
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HCR_E2H | // VHE mode (forced)
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HCR_RW | // AArch64 guest
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HCR_AMO | // Trap SError exceptions
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HCR_VM); // Enable stage 2 translation
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2021-05-04 10:36:23 +00:00
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// No guest vectors initially
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msr(VBAR_EL12, 0);
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2021-05-25 11:04:20 +00:00
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// Compute tick interval
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hv_tick_interval = mrs(CNTFRQ_EL0) / HV_TICK_RATE;
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2021-05-01 10:05:21 +00:00
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sysop("dsb ishst");
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sysop("tlbi alle1is");
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sysop("dsb ish");
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sysop("isb");
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}
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2021-05-04 10:36:23 +00:00
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void hv_start(void *entry, u64 regs[4])
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{
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msr(VBAR_EL1, _hv_vectors_start);
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2021-05-25 11:04:20 +00:00
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hv_arm_tick();
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2021-05-04 10:36:23 +00:00
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hv_enter_guest(regs[0], regs[1], regs[2], regs[3], entry);
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2021-05-04 15:24:52 +00:00
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printf("Exiting hypervisor.\n");
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2021-05-04 10:36:23 +00:00
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}
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2021-05-25 11:04:20 +00:00
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void hv_arm_tick(void)
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{
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msr(CNTP_TVAL_EL0, hv_tick_interval);
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msr(CNTP_CTL_EL0, CNTx_CTL_ENABLE);
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}
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void hv_tick(void)
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{
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// printf("HV tick!\n");
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}
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