2021-01-12 18:22:11 +00:00
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/* SPDX-License-Identifier: MIT */
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#define UART_BASE 0x235200000
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#define UTRSTAT 0x010
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#define UTXH 0x020
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2021-01-16 15:45:10 +00:00
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#define WDT_BASE 0x23d2b0000
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#define WDT_COUNT 0x10
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#define WDT_ALARM 0x14
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#define WDT_CTL 0x1c
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2021-01-12 18:22:11 +00:00
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.extern _start_c
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.extern _stack_bot
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2021-01-16 15:45:10 +00:00
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.extern _v_sp0_sync
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.extern _v_sp0_irq
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.extern _v_sp0_fiq
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.extern _v_sp0_serr
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2021-01-28 07:05:24 +00:00
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.extern _reset_stack
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.extern _cpu_reset_c
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2021-01-12 18:22:11 +00:00
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.section .init, "ax"
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2021-01-16 15:45:10 +00:00
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.globl _vectors_start
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_vectors_start:
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mov x9, '0'
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2021-01-28 07:05:24 +00:00
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b cpu_reset
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2021-01-16 15:45:10 +00:00
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.align 7
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mov x9, '1'
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b exc_unk
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.align 7
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mov x9, '2'
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b exc_unk
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.align 7
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mov x9, '3'
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b exc_unk
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.align 7
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b _v_sp0_sync
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.align 7
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b _v_sp0_irq
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.align 7
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b _v_sp0_fiq
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.align 7
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b _v_sp0_serr
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.align 7
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mov x9, 'a'
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b exc_unk
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.align 7
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mov x9, 'b'
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b exc_unk
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.align 7
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mov x9, 'c'
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b exc_unk
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.align 7
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mov x9, 'd'
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b exc_unk
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.align 7
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mov x9, 'p'
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b exc_unk
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.align 7
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mov x9, 'q'
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b exc_unk
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.align 7
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mov x9, 'r'
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b exc_unk
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.align 7
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mov x9, 's'
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b exc_unk
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.align 7
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2021-01-12 18:22:11 +00:00
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.globl _start
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.type _start, @function
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_start:
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2021-01-17 14:16:58 +00:00
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mov x19, x0
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2021-01-12 18:22:11 +00:00
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mov w0, 'm'
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bl debug_putc
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2021-01-28 07:05:24 +00:00
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2021-01-28 14:32:30 +00:00
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adrp x1, _stack_bot
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mov sp, x1
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2021-01-12 18:22:11 +00:00
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mov w0, '1'
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bl debug_putc
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2021-01-28 14:32:30 +00:00
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ldr x2, [sp, #-8]
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2021-01-28 07:05:24 +00:00
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2021-01-12 18:22:11 +00:00
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mov w0, 'n'
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bl debug_putc
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adrp x0, _base
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mov x20, x0
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adrp x1, _rela_start
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add x1, x1, :lo12:_rela_start
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adrp x2, _rela_end
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add x2, x2, :lo12:_rela_end
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bl apply_rela
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mov w0, '1'
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bl debug_putc
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2021-01-17 14:17:30 +00:00
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mov w0, 0xd /* '\r', clang compat */
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2021-01-12 18:22:11 +00:00
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bl debug_putc
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mov w0, '\n'
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bl debug_putc
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2021-01-28 07:05:24 +00:00
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2021-01-17 14:16:58 +00:00
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mov x0, x19
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mov x1, x20
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2021-01-12 18:22:11 +00:00
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bl _start_c
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b .
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2021-01-16 15:45:10 +00:00
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.globl exc_unk
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.type exc_unk, @function
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exc_unk:
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mov w0, 0xd /* '\r', clang compat */
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2021-01-16 15:45:10 +00:00
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bl debug_putc
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mov w0, '\n'
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bl debug_putc
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mov w0, '!'
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bl debug_putc
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mov w0, 'E'
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bl debug_putc
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mov w0, 'x'
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bl debug_putc
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mov w0, 'C'
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bl debug_putc
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mov w0, ':'
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bl debug_putc
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mov w0, w9
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bl debug_putc
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mov w0, '!'
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bl debug_putc
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2021-01-17 14:17:30 +00:00
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mov w0, 0xd /* '\r', clang compat */
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2021-01-16 15:45:10 +00:00
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bl debug_putc
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mov w0, '\n'
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bl debug_putc
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b reboot
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2021-01-28 07:05:24 +00:00
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.globl cpu_reset
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.type cpu_reset, @function
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cpu_reset:
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mov w0, 'O'
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bl debug_putc
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adrp x1, _reset_stack
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ldr x1, [x1]
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mov sp, x1
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2021-01-28 14:32:30 +00:00
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ldr x2, [sp, #-8]
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2021-01-28 07:05:24 +00:00
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mov w0, 'K'
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bl debug_putc
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bl _cpu_reset_c
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b .
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2021-01-12 18:22:11 +00:00
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.globl debug_putc
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.type debug_putc, @function
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debug_putc:
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ldr x1, =UART_BASE
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1:
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ldr w2, [x1, UTRSTAT]
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tst w2, #2
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beq 1b
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str w0, [x1, UTXH]
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ret
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2021-01-16 15:45:10 +00:00
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.globl reboot
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.type reboot, @function
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reboot:
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ldr x1, =WDT_BASE
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mov w0, #0x100000
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str w0, [x1, #WDT_ALARM]
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mov w0, #0
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str w0, [x1, #WDT_COUNT]
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mov w0, #4
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str w0, [x1, #WDT_CTL]
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b .
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.pool
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