mirror of
https://github.com/yuzu-mirror/yuzu
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521 lines
18 KiB
C++
521 lines
18 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include <initializer_list>
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#include <map>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "core/mem_map.h"
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namespace Pica {
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// Returns index corresponding to the Regs member labeled by field_name
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// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
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// when used with array elements (e.g. PICA_REG_INDEX(vs_uniform_setup.set_value[1])).
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// For details cf. https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
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// Hopefully, this will be fixed sometime in the future.
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// For lack of better alternatives, we currently hardcode the offsets when constant
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// expressions are needed via PICA_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
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// will then make sure the offsets indeed match the automatically calculated ones).
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#define PICA_REG_INDEX(field_name) (offsetof(Pica::Regs, field_name) / sizeof(u32))
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#if defined(_MSC_VER)
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#define PICA_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) (backup_workaround_index)
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#else
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// NOTE: Yeah, hacking in a static_assert here just to workaround the lacking MSVC compiler
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// really is this annoying. This macro just forwards its first argument to PICA_REG_INDEX
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// and then performs a (no-op) cast to size_t iff the second argument matches the expected
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// field offset. Otherwise, the compiler will fail to compile this code.
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#define PICA_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
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((typename std::enable_if<backup_workaround_index == PICA_REG_INDEX(field_name), size_t>::type)PICA_REG_INDEX(field_name))
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#endif // _MSC_VER
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struct Regs {
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// helper macro to properly align structure members.
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// Calling INSERT_PADDING_WORDS will add a new member variable with a name like "pad121",
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// depending on the current source line to make sure variable names are unique.
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#define INSERT_PADDING_WORDS_HELPER1(x, y) x ## y
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#define INSERT_PADDING_WORDS_HELPER2(x, y) INSERT_PADDING_WORDS_HELPER1(x, y)
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#define INSERT_PADDING_WORDS(num_words) u32 INSERT_PADDING_WORDS_HELPER2(pad, __LINE__)[(num_words)];
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INSERT_PADDING_WORDS(0x41);
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BitField<0, 24, u32> viewport_size_x;
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 24, u32> viewport_size_y;
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INSERT_PADDING_WORDS(0x9);
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BitField<0, 24, u32> viewport_depth_range; // float24
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BitField<0, 24, u32> viewport_depth_far_plane; // float24
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INSERT_PADDING_WORDS(0x1);
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union {
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// Maps components of output vertex attributes to semantics
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enum Semantic : u32
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{
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POSITION_X = 0,
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POSITION_Y = 1,
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POSITION_Z = 2,
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POSITION_W = 3,
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COLOR_R = 8,
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COLOR_G = 9,
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COLOR_B = 10,
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COLOR_A = 11,
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TEXCOORD0_U = 12,
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TEXCOORD0_V = 13,
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TEXCOORD1_U = 14,
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TEXCOORD1_V = 15,
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TEXCOORD2_U = 22,
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TEXCOORD2_V = 23,
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INVALID = 31,
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};
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BitField< 0, 5, Semantic> map_x;
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BitField< 8, 5, Semantic> map_y;
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BitField<16, 5, Semantic> map_z;
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BitField<24, 5, Semantic> map_w;
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} vs_output_attributes[7];
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INSERT_PADDING_WORDS(0x11);
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union {
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BitField< 0, 16, u32> x;
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BitField<16, 16, u32> y;
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} viewport_corner;
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INSERT_PADDING_WORDS(0x197);
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struct {
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enum class Format : u64 {
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BYTE = 0,
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UBYTE = 1,
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SHORT = 2,
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FLOAT = 3,
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};
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BitField<0, 29, u32> base_address;
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inline u32 GetBaseAddress() const {
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// TODO: Ugly, should fix PhysicalToVirtualAddress instead
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return DecodeAddressRegister(base_address) - Memory::FCRAM_PADDR + Memory::HEAP_GSP_VADDR;
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}
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// Descriptor for internal vertex attributes
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union {
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BitField< 0, 2, Format> format0; // size of one element
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BitField< 2, 2, u64> size0; // number of elements minus 1
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BitField< 4, 2, Format> format1;
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BitField< 6, 2, u64> size1;
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BitField< 8, 2, Format> format2;
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BitField<10, 2, u64> size2;
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BitField<12, 2, Format> format3;
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BitField<14, 2, u64> size3;
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BitField<16, 2, Format> format4;
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BitField<18, 2, u64> size4;
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BitField<20, 2, Format> format5;
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BitField<22, 2, u64> size5;
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BitField<24, 2, Format> format6;
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BitField<26, 2, u64> size6;
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BitField<28, 2, Format> format7;
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BitField<30, 2, u64> size7;
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BitField<32, 2, Format> format8;
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BitField<34, 2, u64> size8;
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BitField<36, 2, Format> format9;
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BitField<38, 2, u64> size9;
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BitField<40, 2, Format> format10;
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BitField<42, 2, u64> size10;
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BitField<44, 2, Format> format11;
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BitField<46, 2, u64> size11;
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BitField<48, 12, u64> attribute_mask;
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// number of total attributes minus 1
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BitField<60, 4, u64> num_extra_attributes;
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};
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inline Format GetFormat(int n) const {
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Format formats[] = {
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format0, format1, format2, format3,
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format4, format5, format6, format7,
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format8, format9, format10, format11
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};
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return formats[n];
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}
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inline int GetNumElements(int n) const {
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u64 sizes[] = {
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size0, size1, size2, size3,
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size4, size5, size6, size7,
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size8, size9, size10, size11
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};
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return (int)sizes[n]+1;
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}
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inline int GetElementSizeInBytes(int n) const {
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return (GetFormat(n) == Format::FLOAT) ? 4 :
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(GetFormat(n) == Format::SHORT) ? 2 : 1;
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}
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inline int GetStride(int n) const {
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return GetNumElements(n) * GetElementSizeInBytes(n);
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}
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inline int GetNumTotalAttributes() const {
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return (int)num_extra_attributes+1;
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}
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// Attribute loaders map the source vertex data to input attributes
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// This e.g. allows to load different attributes from different memory locations
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struct {
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// Source attribute data offset from the base address
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u32 data_offset;
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union {
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BitField< 0, 4, u64> comp0;
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BitField< 4, 4, u64> comp1;
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BitField< 8, 4, u64> comp2;
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BitField<12, 4, u64> comp3;
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BitField<16, 4, u64> comp4;
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BitField<20, 4, u64> comp5;
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BitField<24, 4, u64> comp6;
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BitField<28, 4, u64> comp7;
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BitField<32, 4, u64> comp8;
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BitField<36, 4, u64> comp9;
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BitField<40, 4, u64> comp10;
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BitField<44, 4, u64> comp11;
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// bytes for a single vertex in this loader
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BitField<48, 8, u64> byte_count;
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BitField<60, 4, u64> component_count;
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};
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inline int GetComponent(int n) const {
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u64 components[] = {
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comp0, comp1, comp2, comp3,
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comp4, comp5, comp6, comp7,
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comp8, comp9, comp10, comp11
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};
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return (int)components[n];
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}
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} attribute_loaders[12];
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} vertex_attributes;
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struct {
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enum IndexFormat : u32 {
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BYTE = 0,
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SHORT = 1,
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};
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union {
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BitField<0, 31, u32> offset; // relative to base attribute address
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BitField<31, 1, IndexFormat> format;
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};
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} index_array;
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// Number of vertices to render
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u32 num_vertices;
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INSERT_PADDING_WORDS(0x5);
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// These two trigger rendering of triangles
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u32 trigger_draw;
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u32 trigger_draw_indexed;
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INSERT_PADDING_WORDS(0x2e);
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enum class TriangleTopology : u32 {
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List = 0,
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Strip = 1,
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Fan = 2,
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ListIndexed = 3, // TODO: No idea if this is correct
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};
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BitField<8, 2, TriangleTopology> triangle_topology;
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INSERT_PADDING_WORDS(0x5b);
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// Offset to shader program entry point (in words)
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BitField<0, 16, u32> vs_main_offset;
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union {
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BitField< 0, 4, u64> attribute0_register;
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BitField< 4, 4, u64> attribute1_register;
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BitField< 8, 4, u64> attribute2_register;
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BitField<12, 4, u64> attribute3_register;
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BitField<16, 4, u64> attribute4_register;
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BitField<20, 4, u64> attribute5_register;
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BitField<24, 4, u64> attribute6_register;
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BitField<28, 4, u64> attribute7_register;
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BitField<32, 4, u64> attribute8_register;
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BitField<36, 4, u64> attribute9_register;
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BitField<40, 4, u64> attribute10_register;
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BitField<44, 4, u64> attribute11_register;
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BitField<48, 4, u64> attribute12_register;
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BitField<52, 4, u64> attribute13_register;
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BitField<56, 4, u64> attribute14_register;
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BitField<60, 4, u64> attribute15_register;
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int GetRegisterForAttribute(int attribute_index) {
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u64 fields[] = {
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attribute0_register, attribute1_register, attribute2_register, attribute3_register,
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attribute4_register, attribute5_register, attribute6_register, attribute7_register,
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attribute8_register, attribute9_register, attribute10_register, attribute11_register,
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attribute12_register, attribute13_register, attribute14_register, attribute15_register,
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};
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return (int)fields[attribute_index];
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}
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} vs_input_register_map;
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INSERT_PADDING_WORDS(0x3);
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struct {
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enum Format : u32
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{
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FLOAT24 = 0,
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FLOAT32 = 1
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};
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bool IsFloat32() const {
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return format == FLOAT32;
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}
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union {
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// Index of the next uniform to write to
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// TODO: ctrulib uses 8 bits for this, however that seems to yield lots of invalid indices
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BitField<0, 7, u32> index;
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BitField<31, 1, Format> format;
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};
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// Writing to these registers sets the "current" uniform.
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// TODO: It's not clear how the hardware stores what the "current" uniform is.
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u32 set_value[8];
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} vs_uniform_setup;
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INSERT_PADDING_WORDS(0x2);
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struct {
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u32 begin_load;
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// Writing to these registers sets the "current" word in the shader program.
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// TODO: It's not clear how the hardware stores what the "current" word is.
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u32 set_word[8];
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} vs_program;
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INSERT_PADDING_WORDS(0x1);
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// This register group is used to load an internal table of swizzling patterns,
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// which are indexed by each shader instruction to specify vector component swizzling.
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struct {
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u32 begin_load;
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// Writing to these registers sets the "current" swizzle pattern in the table.
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// TODO: It's not clear how the hardware stores what the "current" swizzle pattern is.
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u32 set_word[8];
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} vs_swizzle_patterns;
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INSERT_PADDING_WORDS(0x22);
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#undef INSERT_PADDING_WORDS_HELPER1
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#undef INSERT_PADDING_WORDS_HELPER2
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#undef INSERT_PADDING_WORDS
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// Map register indices to names readable by humans
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// Used for debugging purposes, so performance is not an issue here
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static std::string GetCommandName(int index) {
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std::map<u32, std::string> map;
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Regs regs;
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// TODO: MSVC does not support using offsetof() on non-static data members even though this
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// is technically allowed since C++11. Hence, this functionality is disabled until
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// MSVC properly supports it.
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#ifndef _MSC_VER
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#define ADD_FIELD(name) \
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do { \
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map.insert({PICA_REG_INDEX(name), #name}); \
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for (u32 i = PICA_REG_INDEX(name) + 1; i < PICA_REG_INDEX(name) + sizeof(regs.name) / 4; ++i) \
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map.insert({i, #name + std::string("+") + std::to_string(i-PICA_REG_INDEX(name))}); \
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} while(false)
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ADD_FIELD(viewport_size_x);
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ADD_FIELD(viewport_size_y);
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ADD_FIELD(viewport_depth_range);
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ADD_FIELD(viewport_depth_far_plane);
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ADD_FIELD(viewport_corner);
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ADD_FIELD(vertex_attributes);
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ADD_FIELD(index_array);
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ADD_FIELD(num_vertices);
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ADD_FIELD(trigger_draw);
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_main_offset);
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ADD_FIELD(vs_input_register_map);
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ADD_FIELD(vs_uniform_setup);
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ADD_FIELD(vs_program);
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ADD_FIELD(vs_swizzle_patterns);
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#undef ADD_FIELD
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#endif // _MSC_VER
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// Return empty string if no match is found
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return map[index];
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}
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static inline int NumIds() {
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return sizeof(Regs) / sizeof(u32);
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}
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u32& operator [] (int index) const {
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u32* content = (u32*)this;
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return content[index];
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}
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u32& operator [] (int index) {
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u32* content = (u32*)this;
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return content[index];
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}
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private:
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/*
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* Most physical addresses which Pica registers refer to are 8-byte aligned.
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* This function should be used to get the address from a raw register value.
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*/
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static inline u32 DecodeAddressRegister(u32 register_value) {
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return register_value * 8;
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}
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};
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// TODO: MSVC does not support using offsetof() on non-static data members even though this
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// is technically allowed since C++11. This macro should be enabled once MSVC adds
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// support for that.
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#ifndef _MSC_VER
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#define ASSERT_REG_POSITION(field_name, position) static_assert(offsetof(Regs, field_name) == position * 4, "Field "#field_name" has invalid position")
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ASSERT_REG_POSITION(viewport_size_x, 0x41);
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ASSERT_REG_POSITION(viewport_size_y, 0x43);
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ASSERT_REG_POSITION(viewport_depth_range, 0x4d);
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ASSERT_REG_POSITION(viewport_depth_far_plane, 0x4e);
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ASSERT_REG_POSITION(vs_output_attributes[0], 0x50);
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ASSERT_REG_POSITION(vs_output_attributes[1], 0x51);
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ASSERT_REG_POSITION(viewport_corner, 0x68);
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ASSERT_REG_POSITION(vertex_attributes, 0x200);
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ASSERT_REG_POSITION(index_array, 0x227);
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ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
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ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
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ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
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ASSERT_REG_POSITION(vs_program, 0x2cb);
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ASSERT_REG_POSITION(vs_swizzle_patterns, 0x2d5);
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#undef ASSERT_REG_POSITION
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#endif // !defined(_MSC_VER)
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// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value anyway.
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static_assert(sizeof(Regs) <= 0x300 * sizeof(u32), "Register set structure larger than it should be");
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static_assert(sizeof(Regs) >= 0x300 * sizeof(u32), "Register set structure smaller than it should be");
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extern Regs registers; // TODO: Not sure if we want to have one global instance for this
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struct float24 {
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static float24 FromFloat32(float val) {
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float24 ret;
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ret.value = val;
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return ret;
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}
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// 16 bit mantissa, 7 bit exponent, 1 bit sign
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// TODO: No idea if this works as intended
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static float24 FromRawFloat24(u32 hex) {
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float24 ret;
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if ((hex & 0xFFFFFF) == 0) {
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ret.value = 0;
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} else {
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u32 mantissa = hex & 0xFFFF;
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u32 exponent = (hex >> 16) & 0x7F;
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u32 sign = hex >> 23;
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ret.value = powf(2.0f, (float)exponent-63.0f) * (1.0f + mantissa * powf(2.0f, -16.f));
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if (sign)
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ret.value = -ret.value;
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}
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return ret;
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}
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// Not recommended for anything but logging
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float ToFloat32() const {
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return value;
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}
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float24 operator * (const float24& flt) const {
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return float24::FromFloat32(ToFloat32() * flt.ToFloat32());
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}
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float24 operator / (const float24& flt) const {
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return float24::FromFloat32(ToFloat32() / flt.ToFloat32());
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}
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float24 operator + (const float24& flt) const {
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return float24::FromFloat32(ToFloat32() + flt.ToFloat32());
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}
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float24 operator - (const float24& flt) const {
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return float24::FromFloat32(ToFloat32() - flt.ToFloat32());
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}
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float24 operator - () const {
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return float24::FromFloat32(-ToFloat32());
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}
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bool operator < (const float24& flt) const {
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return ToFloat32() < flt.ToFloat32();
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|
}
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|
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bool operator > (const float24& flt) const {
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|
return ToFloat32() > flt.ToFloat32();
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|
}
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|
|
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bool operator >= (const float24& flt) const {
|
|
return ToFloat32() >= flt.ToFloat32();
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|
}
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|
|
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bool operator <= (const float24& flt) const {
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|
return ToFloat32() <= flt.ToFloat32();
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|
}
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|
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private:
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float24() = default;
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|
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// Stored as a regular float, merely for convenience
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|
// TODO: Perform proper arithmetic on this!
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|
float value;
|
|
};
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|
|
|
union CommandHeader {
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|
CommandHeader(u32 h) : hex(h) {}
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|
|
|
u32 hex;
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|
|
|
BitField< 0, 16, u32> cmd_id;
|
|
BitField<16, 4, u32> parameter_mask;
|
|
BitField<20, 11, u32> extra_data_length;
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|
BitField<31, 1, u32> group_commands;
|
|
};
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|
|
|
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} // namespace
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