mirror of
https://github.com/yuzu-mirror/yuzu
synced 2024-12-30 10:23:05 +00:00
Change texture_cache chaching from GPUAddr to CacheAddr
This also reverses the changes to make invalidation and flushing through the GPU address.
This commit is contained in:
parent
b711cdce78
commit
d86f9cd709
7 changed files with 60 additions and 101 deletions
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@ -69,7 +69,7 @@ GPUVAddr MemoryManager::UnmapBuffer(GPUVAddr gpu_addr, u64 size) {
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const u64 aligned_size{Common::AlignUp(size, page_size)};
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const CacheAddr cache_addr{ToCacheAddr(GetPointer(gpu_addr))};
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rasterizer.FlushAndInvalidateRegionEx(gpu_addr, cache_addr, aligned_size);
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rasterizer.FlushAndInvalidateRegion(cache_addr, aligned_size);
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UnmapRange(gpu_addr, aligned_size);
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return gpu_addr;
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@ -49,10 +49,6 @@ public:
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/// and invalidated
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virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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/// and invalidated
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virtual void FlushAndInvalidateRegionEx(GPUVAddr gpu_addr, CacheAddr addr, u64 size) = 0;
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/// Attempt to use a faster method to perform a surface copy
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virtual bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
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const Tegra::Engines::Fermi2D::Regs::Surface& dst,
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@ -737,27 +737,11 @@ void RasterizerOpenGL::InvalidateRegion(CacheAddr addr, u64 size) {
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buffer_cache.InvalidateRegion(addr, size);
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}
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void RasterizerOpenGL::InvalidateRegionEx(GPUVAddr gpu_addr, CacheAddr addr, u64 size) {
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MICROPROFILE_SCOPE(OpenGL_CacheManagement);
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if (!addr || !size) {
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return;
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}
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texture_cache.InvalidateRegionEx(gpu_addr, size);
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shader_cache.InvalidateRegion(addr, size);
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global_cache.InvalidateRegion(addr, size);
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buffer_cache.InvalidateRegion(addr, size);
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}
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void RasterizerOpenGL::FlushAndInvalidateRegion(CacheAddr addr, u64 size) {
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FlushRegion(addr, size);
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InvalidateRegion(addr, size);
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}
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void RasterizerOpenGL::FlushAndInvalidateRegionEx(GPUVAddr gpu_addr, CacheAddr addr, u64 size) {
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FlushRegion(addr, size);
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InvalidateRegionEx(gpu_addr, addr, size);
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}
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bool RasterizerOpenGL::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
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const Tegra::Engines::Fermi2D::Regs::Surface& dst,
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const Common::Rectangle<u32>& src_rect,
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@ -64,9 +64,7 @@ public:
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void FlushAll() override;
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void FlushRegion(CacheAddr addr, u64 size) override;
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void InvalidateRegion(CacheAddr addr, u64 size) override;
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void InvalidateRegionEx(GPUVAddr gpu_addr, CacheAddr addr, u64 size);
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void FlushAndInvalidateRegion(CacheAddr addr, u64 size) override;
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void FlushAndInvalidateRegionEx(GPUVAddr gpu_addr, CacheAddr addr, u64 size) override;
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bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
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const Tegra::Engines::Fermi2D::Regs::Surface& dst,
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const Common::Rectangle<u32>& src_rect,
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@ -25,7 +25,6 @@ SurfaceBaseImpl::SurfaceBaseImpl(const GPUVAddr gpu_vaddr, const SurfaceParams&
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u32 offset = 0;
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mipmap_offsets.resize(params.num_levels);
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mipmap_sizes.resize(params.num_levels);
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gpu_addr_end = gpu_addr + memory_size;
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for (u32 i = 0; i < params.num_levels; i++) {
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mipmap_offsets[i] = offset;
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mipmap_sizes[i] = params.GetGuestMipmapSize(i);
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@ -99,8 +98,10 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
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}
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}
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void SurfaceBaseImpl::FlushBuffer(std::vector<u8>& staging_buffer) {
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void SurfaceBaseImpl::FlushBuffer(Tegra::MemoryManager& memory_manager,
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std::vector<u8>& staging_buffer) {
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MICROPROFILE_SCOPE(GPU_Flush_Texture);
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auto host_ptr = memory_manager.GetPointer(gpu_addr);
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if (params.is_tiled) {
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ASSERT_MSG(params.block_width == 1, "Block width is defined as {}", params.block_width);
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for (u32 level = 0; level < params.num_levels; ++level) {
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@ -45,40 +45,40 @@ class SurfaceBaseImpl {
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public:
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void LoadBuffer(Tegra::MemoryManager& memory_manager, std::vector<u8>& staging_buffer);
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void FlushBuffer(std::vector<u8>& staging_buffer);
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void FlushBuffer(Tegra::MemoryManager& memory_manager, std::vector<u8>& staging_buffer);
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GPUVAddr GetGpuAddr() const {
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return gpu_addr;
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}
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GPUVAddr GetGpuAddrEnd() const {
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return gpu_addr_end;
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}
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bool Overlaps(const GPUVAddr start, const GPUVAddr end) const {
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return (gpu_addr < end) && (gpu_addr_end > start);
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bool Overlaps(const CacheAddr start, const CacheAddr end) const {
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return (cache_addr < end) && (cache_addr_end > start);
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}
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// Use only when recycling a surface
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void SetGpuAddr(const GPUVAddr new_addr) {
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gpu_addr = new_addr;
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gpu_addr_end = new_addr + memory_size;
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}
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VAddr GetCpuAddr() const {
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return gpu_addr;
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return cpu_addr;
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}
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void SetCpuAddr(const VAddr new_addr) {
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cpu_addr = new_addr;
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}
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u8* GetHostPtr() const {
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return host_ptr;
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CacheAddr GetCacheAddr() const {
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return cache_addr;
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}
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void SetHostPtr(u8* new_addr) {
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host_ptr = new_addr;
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CacheAddr GetCacheAddrEnd() const {
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return cache_addr_end;
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}
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void SetCacheAddr(const CacheAddr new_addr) {
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cache_addr = new_addr;
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cache_addr_end = new_addr + memory_size;
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}
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const SurfaceParams& GetSurfaceParams() const {
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@ -201,13 +201,13 @@ protected:
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const SurfaceParams params;
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GPUVAddr gpu_addr{};
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GPUVAddr gpu_addr_end{};
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std::vector<u32> mipmap_sizes;
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std::vector<u32> mipmap_offsets;
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const std::size_t layer_size;
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const std::size_t memory_size;
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const std::size_t host_memory_size;
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u8* host_ptr;
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CacheAddr cache_addr;
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CacheAddr cache_addr_end{};
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VAddr cpu_addr;
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private:
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@ -60,12 +60,6 @@ public:
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}
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}
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void InvalidateRegionEx(GPUVAddr addr, std::size_t size) {
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for (const auto& surface : GetSurfacesInRegionInner(addr, size)) {
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Unregister(surface);
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}
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}
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TView GetTextureSurface(const Tegra::Texture::FullTextureInfo& config,
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const VideoCommon::Shader::Sampler& entry) {
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const auto gpu_addr{config.tic.Address()};
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@ -154,9 +148,19 @@ public:
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return GetSurface(gpu_addr, params, true).second;
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}
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TSurface TryFindFramebufferSurface(const u8* host_ptr) const {
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const auto it{registered_surfaces.find(ToCacheAddr(host_ptr))};
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return it != registered_surfaces.end() ? *it->second.begin() : nullptr;
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TSurface TryFindFramebufferSurface(const u8* host_ptr) {
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const CacheAddr cache_addr = ToCacheAddr(host_ptr);
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if (!cache_addr) {
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return nullptr;
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}
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const CacheAddr page = cache_addr >> registry_page_bits;
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std::list<TSurface>& list = registry[page];
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for (auto& s : list) {
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if (s->GetCacheAddr() == cache_addr) {
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return s;
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}
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}
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return nullptr;
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}
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u64 Tick() {
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@ -181,30 +185,28 @@ protected:
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void Register(TSurface surface) {
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const GPUVAddr gpu_addr = surface->GetGpuAddr();
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u8* host_ptr = memory_manager->GetPointer(gpu_addr);
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const CacheAddr cache_ptr = ToCacheAddr(memory_manager->GetPointer(gpu_addr));
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const std::size_t size = surface->GetSizeInBytes();
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const std::optional<VAddr> cpu_addr = memory_manager->GpuToCpuAddress(gpu_addr);
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if (!host_ptr || !cpu_addr) {
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if (!cache_ptr || !cpu_addr) {
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LOG_CRITICAL(HW_GPU, "Failed to register surface with unmapped gpu_address 0x{:016x}",
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gpu_addr);
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return;
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}
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surface->SetHostPtr(host_ptr);
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surface->SetCacheAddr(cache_ptr);
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surface->SetCpuAddr(*cpu_addr);
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registered_surfaces.add({GetInterval(host_ptr, size), {surface}});
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rasterizer.UpdatePagesCachedCount(*cpu_addr, size, 1);
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RegisterInnerCache(surface);
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surface->MarkAsRegistered(true);
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rasterizer.UpdatePagesCachedCount(*cpu_addr, size, 1);
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}
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void Unregister(TSurface surface) {
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if (surface->IsProtected())
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return;
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const GPUVAddr gpu_addr = surface->GetGpuAddr();
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const void* host_ptr = surface->GetHostPtr();
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const CacheAddr cache_ptr = surface->GetCacheAddr();
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const std::size_t size = surface->GetSizeInBytes();
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const VAddr cpu_addr = surface->GetCpuAddr();
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registered_surfaces.erase(GetInterval(host_ptr, size));
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rasterizer.UpdatePagesCachedCount(cpu_addr, size, -1);
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UnregisterInnerCache(surface);
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surface->MarkAsRegistered(false);
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@ -280,7 +282,7 @@ private:
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}
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}
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std::pair<TSurface, TView> RebuildMirage(TSurface current_surface,
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std::pair<TSurface, TView> RebuildSurface(TSurface current_surface,
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const SurfaceParams& params) {
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const auto gpu_addr = current_surface->GetGpuAddr();
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TSurface new_surface = GetUncachedSurface(gpu_addr, params);
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@ -297,7 +299,7 @@ private:
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const SurfaceParams& params) {
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const bool is_mirage = !current_surface->MatchFormat(params.pixel_format);
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if (is_mirage) {
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return RebuildMirage(current_surface, params);
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return RebuildSurface(current_surface, params);
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}
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const bool matches_target = current_surface->MatchTarget(params.target);
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if (matches_target) {
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@ -356,7 +358,7 @@ private:
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const auto host_ptr{memory_manager->GetPointer(gpu_addr)};
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const auto cache_addr{ToCacheAddr(host_ptr)};
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const std::size_t candidate_size = params.GetGuestSizeInBytes();
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auto overlaps{GetSurfacesInRegionInner(gpu_addr, candidate_size)};
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auto overlaps{GetSurfacesInRegion(cache_addr, candidate_size)};
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if (overlaps.empty()) {
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return InitializeSurface(gpu_addr, params, preserve_contents);
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}
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@ -378,7 +380,7 @@ private:
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if (s_result == MatchStructureResult::FullMatch) {
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return ManageStructuralMatch(current_surface, params);
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} else {
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return RebuildMirage(current_surface, params);
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return RebuildSurface(current_surface, params);
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}
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}
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if (current_surface->GetSizeInBytes() <= candidate_size) {
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@ -429,58 +431,40 @@ private:
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}
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staging_buffer.resize(surface->GetHostSizeInBytes());
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surface->DownloadTexture(staging_buffer);
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surface->FlushBuffer(staging_buffer);
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surface->FlushBuffer(*memory_manager, staging_buffer);
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surface->MarkAsModified(false, Tick());
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}
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std::vector<TSurface> GetSurfacesInRegion(CacheAddr cache_addr, std::size_t size) const {
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if (size == 0) {
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return {};
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}
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const IntervalType interval{cache_addr, cache_addr + size};
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std::vector<TSurface> surfaces;
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for (auto& pair : boost::make_iterator_range(registered_surfaces.equal_range(interval))) {
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for (auto& s : pair.second) {
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if (!s || !s->IsRegistered()) {
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continue;
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}
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surfaces.push_back(s);
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}
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}
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return surfaces;
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}
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void RegisterInnerCache(TSurface& surface) {
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GPUVAddr start = surface->GetGpuAddr() >> inner_cache_page_bits;
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const GPUVAddr end = (surface->GetGpuAddrEnd() - 1) >> inner_cache_page_bits;
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CacheAddr start = surface->GetCacheAddr() >> registry_page_bits;
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const CacheAddr end = (surface->GetCacheAddrEnd() - 1) >> registry_page_bits;
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while (start <= end) {
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inner_cache[start].push_back(surface);
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registry[start].push_back(surface);
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start++;
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}
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}
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void UnregisterInnerCache(TSurface& surface) {
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GPUVAddr start = surface->GetGpuAddr() >> inner_cache_page_bits;
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const GPUVAddr end = (surface->GetGpuAddrEnd() - 1) >> inner_cache_page_bits;
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CacheAddr start = surface->GetCacheAddr() >> registry_page_bits;
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const CacheAddr end = (surface->GetCacheAddrEnd() - 1) >> registry_page_bits;
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while (start <= end) {
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inner_cache[start].remove(surface);
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registry[start].remove(surface);
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start++;
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}
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}
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std::vector<TSurface> GetSurfacesInRegionInner(const GPUVAddr gpu_addr, const std::size_t size) {
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std::vector<TSurface> GetSurfacesInRegion(const CacheAddr cache_addr, const std::size_t size) {
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if (size == 0) {
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return {};
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}
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const GPUVAddr gpu_addr_end = gpu_addr + size;
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GPUVAddr start = gpu_addr >> inner_cache_page_bits;
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const GPUVAddr end = (gpu_addr_end - 1) >> inner_cache_page_bits;
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const CacheAddr cache_addr_end = cache_addr + size;
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CacheAddr start = cache_addr >> registry_page_bits;
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const CacheAddr end = (cache_addr_end - 1) >> registry_page_bits;
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std::vector<TSurface> surfaces;
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while (start <= end) {
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std::list<TSurface>& list = inner_cache[start];
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std::list<TSurface>& list = registry[start];
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for (auto& s : list) {
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if (!s->IsPicked() && s->Overlaps(gpu_addr, gpu_addr_end)) {
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if (!s->IsPicked() && s->Overlaps(cache_addr, cache_addr_end)) {
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s->MarkAsPicked(true);
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surfaces.push_back(s);
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}
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@ -510,11 +494,6 @@ private:
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return {};
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}
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IntervalType GetInterval(const void* host_ptr, const std::size_t size) const {
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const CacheAddr addr = ToCacheAddr(host_ptr);
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return IntervalType::right_open(addr, addr + size);
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}
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struct RenderInfo {
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RenderTargetConfig config;
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TSurface target;
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@ -531,11 +510,12 @@ private:
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u64 ticks{};
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IntervalMap registered_surfaces;
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static constexpr u64 inner_cache_page_bits{20};
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static constexpr u64 inner_cache_page_size{1 << inner_cache_page_bits};
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std::unordered_map<GPUVAddr, std::list<TSurface>> inner_cache;
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// The internal Cache is different for the Texture Cache. It's based on buckets
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// of 1MB. This fits better for the purpose of this cache as textures are normaly
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// large in size.
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static constexpr u64 registry_page_bits{20};
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static constexpr u64 registry_page_size{1 << registry_page_bits};
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std::unordered_map<CacheAddr, std::list<TSurface>> registry;
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/// The surface reserve is a "backup" cache, this is where we put unique surfaces that have
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/// previously been used. This is to prevent surfaces from being constantly created and
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