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https://github.com/yuzu-mirror/yuzu
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shader: Add support for fp16 comparisons and misc fixes
This commit is contained in:
parent
27fb97377e
commit
a77e764726
11 changed files with 56 additions and 14 deletions
src/shader_recompiler
backend/spirv
frontend
ir
maxwell/translate/impl
ir_opt
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@ -234,7 +234,9 @@ Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPIsNan16(EmitContext& ctx, Id value);
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Id EmitFPIsNan32(EmitContext& ctx, Id value);
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Id EmitFPIsNan64(EmitContext& ctx, Id value);
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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void EmitIAdd64(EmitContext& ctx);
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Id EmitISub32(EmitContext& ctx, Id a, Id b);
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@ -346,8 +346,16 @@ Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpFUnordGreaterThanEqual(ctx.U1, lhs, rhs);
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}
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Id EmitFPIsNan16(EmitContext& ctx, Id value) {
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return ctx.OpIsNan(ctx.U1, value);
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}
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Id EmitFPIsNan32(EmitContext& ctx, Id value) {
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return ctx.OpIsNan(ctx.U1, value);
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}
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Id EmitFPIsNan64(EmitContext& ctx, Id value) {
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return ctx.OpIsNan(ctx.U1, value);
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}
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} // namespace Shader::Backend::SPIRV
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@ -895,15 +895,30 @@ U1 IREmitter::FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpC
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}
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}
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U1 IREmitter::FPIsNan(const F32& value) {
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return Inst<U1>(Opcode::FPIsNan32, value);
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U1 IREmitter::FPIsNan(const F16F32F64& value) {
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switch (value.Type()) {
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case Type::F16:
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return Inst<U1>(Opcode::FPIsNan16, value);
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case Type::F32:
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return Inst<U1>(Opcode::FPIsNan32, value);
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case Type::F64:
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return Inst<U1>(Opcode::FPIsNan64, value);
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default:
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ThrowInvalidType(value.Type());
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}
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}
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U1 IREmitter::FPOrdered(const F32& lhs, const F32& rhs) {
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U1 IREmitter::FPOrdered(const F16F32F64& lhs, const F16F32F64& rhs) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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return LogicalAnd(LogicalNot(FPIsNan(lhs)), LogicalNot(FPIsNan(rhs)));
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}
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U1 IREmitter::FPUnordered(const F32& lhs, const F32& rhs) {
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U1 IREmitter::FPUnordered(const F16F32F64& lhs, const F16F32F64& rhs) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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return LogicalOr(FPIsNan(lhs), FPIsNan(rhs));
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}
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@ -161,9 +161,9 @@ public:
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FpControl control = {}, bool ordered = true);
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[[nodiscard]] U1 FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
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FpControl control = {}, bool ordered = true);
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[[nodiscard]] U1 FPIsNan(const F32& value);
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[[nodiscard]] U1 FPOrdered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U1 FPUnordered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U1 FPIsNan(const F16F32F64& value);
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[[nodiscard]] U1 FPOrdered(const F16F32F64& lhs, const F16F32F64& rhs);
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[[nodiscard]] U1 FPUnordered(const F16F32F64& lhs, const F16F32F64& rhs);
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[[nodiscard]] F32F64 FPMax(const F32F64& lhs, const F32F64& rhs, FpControl control = {});
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[[nodiscard]] F32F64 FPMin(const F32F64& lhs, const F32F64& rhs, FpControl control = {});
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@ -236,7 +236,9 @@ OPCODE(FPOrdGreaterThanEqual64, U1, F64,
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OPCODE(FPUnordGreaterThanEqual16, U1, F16, F16, )
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OPCODE(FPUnordGreaterThanEqual32, U1, F32, F32, )
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OPCODE(FPUnordGreaterThanEqual64, U1, F64, F64, )
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OPCODE(FPIsNan16, U1, F16, )
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OPCODE(FPIsNan32, U1, F32, )
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OPCODE(FPIsNan64, U1, F64, )
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// Integer operations
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OPCODE(IAdd32, U32, U32, U32, )
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@ -6,7 +6,6 @@
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namespace Shader::Maxwell {
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namespace {
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void HADD2(TranslatorVisitor& v, u64 insn, Merge merge, bool ftz, bool sat, bool abs_a, bool neg_a,
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Swizzle swizzle_a, bool abs_b, bool neg_b, Swizzle swizzle_b, const IR::U32& src_b) {
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union {
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@ -66,7 +65,7 @@ void HADD2(TranslatorVisitor& v, u64 insn, bool sat, bool abs_b, bool neg_b, Swi
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HADD2(v, insn, hadd2.merge, hadd2.ftz != 0, sat, hadd2.abs_a != 0, hadd2.neg_a != 0,
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hadd2.swizzle_a, abs_b, neg_b, swizzle_b, src_b);
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}
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} // namespace
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} // Anonymous namespace
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void TranslatorVisitor::HADD2_reg(u64 insn) {
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union {
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@ -6,7 +6,6 @@
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namespace Shader::Maxwell {
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namespace {
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void HFMA2(TranslatorVisitor& v, u64 insn, Merge merge, Swizzle swizzle_a, bool neg_b, bool neg_c,
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Swizzle swizzle_b, Swizzle swizzle_c, const IR::U32& src_b, const IR::U32& src_c,
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bool sat, HalfPrecision precision) {
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@ -85,8 +84,7 @@ void HFMA2(TranslatorVisitor& v, u64 insn, bool neg_b, bool neg_c, Swizzle swizz
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HFMA2(v, insn, hfma2.merge, hfma2.swizzle_a, neg_b, neg_c, swizzle_b, swizzle_c, src_b, src_c,
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sat, precision);
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}
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} // namespace
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} // Anonymous namespace
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void TranslatorVisitor::HFMA2_reg(u64 insn) {
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union {
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@ -6,7 +6,6 @@
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namespace Shader::Maxwell {
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namespace {
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void HMUL2(TranslatorVisitor& v, u64 insn, Merge merge, bool sat, bool abs_a, bool neg_a,
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Swizzle swizzle_a, bool abs_b, bool neg_b, Swizzle swizzle_b, const IR::U32& src_b,
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HalfPrecision precision) {
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@ -79,7 +78,7 @@ void HMUL2(TranslatorVisitor& v, u64 insn, bool sat, bool abs_a, bool neg_a, boo
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HMUL2(v, insn, hmul2.merge, sat, abs_a, neg_a, hmul2.swizzle_a, abs_b, neg_b, swizzle_b, src_b,
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hmul2.precision);
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}
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} // namespace
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} // Anonymous namespace
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void TranslatorVisitor::HMUL2_reg(u64 insn) {
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union {
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@ -76,6 +76,7 @@ void TranslatorVisitor::HSET2_reg(u64 insn) {
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BitField<35, 4, FPCompareOp> compare_op;
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BitField<28, 2, Swizzle> swizzle_b;
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} const hset2{insn};
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HSET2(*this, insn, GetReg20(insn), hset2.bf != 0, hset2.ftz != 0, hset2.neg_b != 0,
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hset2.abs_b != 0, hset2.compare_op, hset2.swizzle_b);
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}
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@ -74,6 +74,9 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::CompositeExtractF16x2:
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case IR::Opcode::CompositeExtractF16x3:
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case IR::Opcode::CompositeExtractF16x4:
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case IR::Opcode::CompositeInsertF16x2:
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case IR::Opcode::CompositeInsertF16x3:
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case IR::Opcode::CompositeInsertF16x4:
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case IR::Opcode::SelectF16:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastF16U16:
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@ -103,6 +106,19 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::FPRoundEven16:
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case IR::Opcode::FPSaturate16:
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case IR::Opcode::FPTrunc16:
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case IR::Opcode::FPOrdEqual16:
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case IR::Opcode::FPUnordEqual16:
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case IR::Opcode::FPOrdNotEqual16:
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case IR::Opcode::FPUnordNotEqual16:
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case IR::Opcode::FPOrdLessThan16:
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case IR::Opcode::FPUnordLessThan16:
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case IR::Opcode::FPOrdGreaterThan16:
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case IR::Opcode::FPUnordGreaterThan16:
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case IR::Opcode::FPOrdLessThanEqual16:
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case IR::Opcode::FPUnordLessThanEqual16:
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case IR::Opcode::FPOrdGreaterThanEqual16:
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case IR::Opcode::FPUnordGreaterThanEqual16:
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case IR::Opcode::FPIsNan16:
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info.uses_fp16 = true;
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break;
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case IR::Opcode::FPAbs64:
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@ -74,6 +74,8 @@ IR::Opcode Replace(IR::Opcode op) {
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return IR::Opcode::FPOrdGreaterThanEqual32;
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case IR::Opcode::FPUnordGreaterThanEqual16:
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return IR::Opcode::FPUnordGreaterThanEqual32;
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case IR::Opcode::FPIsNan16:
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return IR::Opcode::FPIsNan32;
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case IR::Opcode::ConvertS16F16:
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return IR::Opcode::ConvertS16F32;
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case IR::Opcode::ConvertS32F16:
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