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https://github.com/yuzu-mirror/yuzu
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Pica/VertexShader: Remove (now) duplicated shader bytecode definitions in favor of nihstro's ones.
This commit is contained in:
Tony Wasserka
parent
056a8f9dfa
commit
8ce1d32460
2 changed files with 30 additions and 222 deletions
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@ -8,11 +8,18 @@
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#include <core/mem_map.h>
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#include <nihstro/shader_bytecode.h>
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#include "debug_utils/debug_utils.h"
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#include "pica.h"
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#include "vertex_shader.h"
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using nihstro::Instruction;
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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using nihstro::SwizzlePattern;
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namespace Pica {
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namespace VertexShader {
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@ -70,19 +77,28 @@ static void ProcessShaderCode(VertexShaderState& state) {
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const Instruction& instr = *(const Instruction*)state.program_counter;
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + (state.program_counter - shader_memory));
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const float24* src1_ = (instr.common.src1 < 0x10) ? state.input_register_table[instr.common.src1.GetIndex()]
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: (instr.common.src1 < 0x20) ? &state.temporary_registers[instr.common.src1.GetIndex()].x
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: (instr.common.src1 < 0x80) ? &shader_uniforms.f[instr.common.src1.GetIndex()].x
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: nullptr;
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const float24* src2_ = (instr.common.src2 < 0x10) ? state.input_register_table[instr.common.src2.GetIndex()]
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: &state.temporary_registers[instr.common.src2.GetIndex()].x;
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auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
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switch (source_reg.GetRegisterType()) {
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case RegisterType::Input:
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return state.input_register_table[source_reg.GetIndex()];
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case RegisterType::Temporary:
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return &state.temporary_registers[source_reg.GetIndex()].x;
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case RegisterType::FloatUniform:
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return &shader_uniforms.f[source_reg.GetIndex()].x;
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}
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};
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bool is_inverted = 0 != (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::SrcInversed);
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const float24* src1_ = LookupSourceRegister(instr.common.GetSrc1(is_inverted));
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const float24* src2_ = LookupSourceRegister(instr.common.GetSrc2(is_inverted));
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float24* dest = (instr.common.dest < 0x08) ? state.output_register_table[4*instr.common.dest.GetIndex()]
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: (instr.common.dest < 0x10) ? nullptr
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: (instr.common.dest < 0x20) ? &state.temporary_registers[instr.common.dest.GetIndex()][0]
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: nullptr;
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
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const bool negate_src1 = (swizzle.negate != 0);
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const bool negate_src1 = (swizzle.negate_src1 != 0);
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float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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@ -192,7 +208,9 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::RET:
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// NOP is currently used as a heuristic for leaving from a function.
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// TODO: This is completely incorrect.
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case Instruction::OpCode::NOP:
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if (*state.call_stack_pointer == VertexShaderState::INVALID_ADDRESS) {
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exit_loop = true;
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} else {
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@ -209,17 +227,16 @@ static void ProcessShaderCode(VertexShaderState& state) {
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_dbg_assert_(HW_GPU, state.call_stack_pointer - state.call_stack < sizeof(state.call_stack));
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*++state.call_stack_pointer = state.program_counter - shader_memory;
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// TODO: Does this offset refer to the beginning of shader memory?
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state.program_counter = &shader_memory[instr.flow_control.offset_words];
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state.program_counter = &shader_memory[instr.flow_control.dest_offset];
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break;
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case Instruction::OpCode::FLS:
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// TODO: Do whatever needs to be done here?
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case Instruction::OpCode::END:
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// TODO
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break;
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default:
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LOG_ERROR(HW_GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.GetOpCodeName().c_str(), instr.hex);
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(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
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break;
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}
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@ -66,215 +66,6 @@ struct OutputVertex {
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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union Instruction {
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enum class OpCode : u32 {
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ADD = 0x0,
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DP3 = 0x1,
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DP4 = 0x2,
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MUL = 0x8,
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MAX = 0xC,
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MIN = 0xD,
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RCP = 0xE,
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RSQ = 0xF,
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MOV = 0x13,
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RET = 0x21,
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FLS = 0x22, // Flush
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CALL = 0x24,
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};
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std::string GetOpCodeName() const {
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std::map<OpCode, std::string> map = {
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{ OpCode::ADD, "ADD" },
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{ OpCode::DP3, "DP3" },
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{ OpCode::DP4, "DP4" },
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{ OpCode::MUL, "MUL" },
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{ OpCode::MAX, "MAX" },
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{ OpCode::MIN, "MIN" },
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{ OpCode::RCP, "RCP" },
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{ OpCode::RSQ, "RSQ" },
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{ OpCode::MOV, "MOV" },
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{ OpCode::RET, "RET" },
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{ OpCode::FLS, "FLS" },
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};
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auto it = map.find(opcode);
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if (it == map.end())
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return "UNK";
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else
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return it->second;
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}
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u32 hex;
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BitField<0x1a, 0x6, OpCode> opcode;
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// General notes:
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//
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// When two input registers are used, one of them uses a 5-bit index while the other
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// one uses a 7-bit index. This is because at most one floating point uniform may be used
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// as an input.
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// Format used e.g. by arithmetic instructions and comparisons
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// "src1" and "src2" specify register indices (i.e. indices referring to groups of 4 floats),
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// while "dest" addresses individual floats.
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union {
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BitField<0x00, 0x5, u32> operand_desc_id;
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template<class BitFieldType>
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struct SourceRegister : BitFieldType {
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enum RegisterType {
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Input,
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Temporary,
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FloatUniform
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};
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RegisterType GetRegisterType() const {
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if (BitFieldType::Value() < 0x10)
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return Input;
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else if (BitFieldType::Value() < 0x20)
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return Temporary;
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else
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return FloatUniform;
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}
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int GetIndex() const {
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if (GetRegisterType() == Input)
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return BitFieldType::Value();
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else if (GetRegisterType() == Temporary)
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return BitFieldType::Value() - 0x10;
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else // if (GetRegisterType() == FloatUniform)
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return BitFieldType::Value() - 0x20;
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}
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std::string GetRegisterName() const {
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std::map<RegisterType, std::string> type = {
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{ Input, "i" },
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{ Temporary, "t" },
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{ FloatUniform, "f" },
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};
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return type[GetRegisterType()] + std::to_string(GetIndex());
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}
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};
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SourceRegister<BitField<0x07, 0x5, u32>> src2;
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SourceRegister<BitField<0x0c, 0x7, u32>> src1;
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struct : BitField<0x15, 0x5, u32>
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{
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enum RegisterType {
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Output,
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Temporary,
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Unknown
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};
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RegisterType GetRegisterType() const {
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if (Value() < 0x8)
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return Output;
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else if (Value() < 0x10)
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return Unknown;
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else
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return Temporary;
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}
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int GetIndex() const {
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if (GetRegisterType() == Output)
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return Value();
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else if (GetRegisterType() == Temporary)
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return Value() - 0x10;
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else
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return Value();
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}
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std::string GetRegisterName() const {
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std::map<RegisterType, std::string> type = {
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{ Output, "o" },
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{ Temporary, "t" },
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{ Unknown, "u" }
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};
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return type[GetRegisterType()] + std::to_string(GetIndex());
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}
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} dest;
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} common;
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// Format used for flow control instructions ("if")
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union {
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BitField<0x00, 0x8, u32> num_instructions;
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BitField<0x0a, 0xc, u32> offset_words;
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} flow_control;
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};
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static_assert(std::is_standard_layout<Instruction>::value, "Structure is not using standard layout!");
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union SwizzlePattern {
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u32 hex;
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enum class Selector : u32 {
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x = 0,
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y = 1,
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z = 2,
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w = 3
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};
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Selector GetSelectorSrc1(int comp) const {
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Selector selectors[] = {
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src1_selector_0, src1_selector_1, src1_selector_2, src1_selector_3
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};
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return selectors[comp];
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}
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Selector GetSelectorSrc2(int comp) const {
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Selector selectors[] = {
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src2_selector_0, src2_selector_1, src2_selector_2, src2_selector_3
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};
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return selectors[comp];
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}
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bool DestComponentEnabled(int i) const {
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return (dest_mask & (0x8 >> i)) != 0;
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}
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std::string SelectorToString(bool src2) const {
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std::map<Selector, std::string> map = {
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{ Selector::x, "x" },
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{ Selector::y, "y" },
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{ Selector::z, "z" },
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{ Selector::w, "w" }
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};
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std::string ret;
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for (int i = 0; i < 4; ++i) {
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ret += map.at(src2 ? GetSelectorSrc2(i) : GetSelectorSrc1(i));
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}
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return ret;
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}
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std::string DestMaskToString() const {
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std::string ret;
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for (int i = 0; i < 4; ++i) {
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if (!DestComponentEnabled(i))
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ret += "_";
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else
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ret += "xyzw"[i];
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}
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return ret;
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}
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// Components of "dest" that should be written to: LSB=dest.w, MSB=dest.x
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BitField< 0, 4, u32> dest_mask;
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BitField< 4, 1, u32> negate; // negates src1
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BitField< 5, 2, Selector> src1_selector_3;
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BitField< 7, 2, Selector> src1_selector_2;
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BitField< 9, 2, Selector> src1_selector_1;
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BitField<11, 2, Selector> src1_selector_0;
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BitField<14, 2, Selector> src2_selector_3;
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BitField<16, 2, Selector> src2_selector_2;
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BitField<18, 2, Selector> src2_selector_1;
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BitField<20, 2, Selector> src2_selector_0;
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BitField<31, 1, u32> flag; // not sure what this means, maybe it's the sign?
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};
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void SubmitShaderMemoryChange(u32 addr, u32 value);
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void SubmitSwizzleDataChange(u32 addr, u32 value);
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