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https://github.com/yuzu-mirror/yuzu
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glsl: Cleanup/Address feedback
This commit is contained in:
parent
74f683787e
commit
6eea88d614
10 changed files with 24 additions and 28 deletions
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@ -156,8 +156,7 @@ void EmitCode(EmitContext& ctx, const IR::Program& program) {
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ctx.Add("for(;;){{");
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ctx.Add("for(;;){{");
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break;
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break;
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case IR::AbstractSyntaxNode::Type::Repeat:
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case IR::AbstractSyntaxNode::Type::Repeat:
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ctx.Add("if({}){{continue;}}else{{break;}}}}",
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ctx.Add("if(!{}){{break;}}}}", ctx.var_alloc.Consume(node.data.repeat.cond));
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ctx.var_alloc.Consume(node.data.repeat.cond));
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break;
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break;
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default:
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default:
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throw NotImplementedException("AbstractSyntaxNode Type {}", node.type);
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throw NotImplementedException("AbstractSyntaxNode Type {}", node.type);
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@ -166,7 +165,7 @@ void EmitCode(EmitContext& ctx, const IR::Program& program) {
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}
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}
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std::string GlslVersionSpecifier(const EmitContext& ctx) {
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std::string GlslVersionSpecifier(const EmitContext& ctx) {
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if (ctx.uses_y_direction || ctx.info.stores_legacy_varyings) {
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if (ctx.uses_y_direction || ctx.info.stores_legacy_varyings || ctx.info.loads_legacy_varyings) {
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return " compatibility";
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return " compatibility";
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}
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}
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return "";
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return "";
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@ -187,7 +186,8 @@ void DefineVariables(const EmitContext& ctx, std::string& header) {
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const auto type{static_cast<GlslVarType>(i)};
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const auto type{static_cast<GlslVarType>(i)};
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const auto& tracker{ctx.var_alloc.GetUseTracker(type)};
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const auto& tracker{ctx.var_alloc.GetUseTracker(type)};
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const auto type_name{ctx.var_alloc.GetGlslType(type)};
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const auto type_name{ctx.var_alloc.GetGlslType(type)};
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const auto precise{IsPreciseType(type) ? "precise " : ""};
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const bool has_precise_bug{ctx.stage == Stage::Fragment && ctx.profile.has_gl_precise_bug};
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const auto precise{!has_precise_bug && IsPreciseType(type) ? "precise " : ""};
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// Temps/return types that are never used are stored at index 0
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// Temps/return types that are never used are stored at index 0
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if (tracker.uses_temp) {
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if (tracker.uses_temp) {
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header += fmt::format("{}{} t{}={}(0);", precise, type_name,
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header += fmt::format("{}{} t{}={}(0);", precise, type_name,
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@ -98,7 +98,7 @@ void EmitSharedAtomicExchange32(EmitContext& ctx, IR::Inst& inst, std::string_vi
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void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, std::string_view pointer_offset,
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void EmitSharedAtomicExchange64(EmitContext& ctx, IR::Inst& inst, std::string_view pointer_offset,
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std::string_view value) {
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std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 Atomics not supported, fallback to non-atomic");
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU64("{}=packUint2x32(uvec2(smem[{}>>2],smem[({}+4)>>2]));", inst, pointer_offset,
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ctx.AddU64("{}=packUint2x32(uvec2(smem[{}>>2],smem[({}+4)>>2]));", inst, pointer_offset,
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pointer_offset);
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pointer_offset);
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ctx.Add("smem[{}>>2]=unpackUint2x32({}).x;smem[({}+4)>>2]=unpackUint2x32({}).y;",
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ctx.Add("smem[{}>>2]=unpackUint2x32({}).x;smem[({}+4)>>2]=unpackUint2x32({}).y;",
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@ -171,7 +171,7 @@ void EmitStorageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Val
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void EmitStorageAtomicIAdd64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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void EmitStorageAtomicIAdd64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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const IR::Value& offset, std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 Atomics not supported, fallback to non-atomic");
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU64("{}=packUint2x32(uvec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.AddU64("{}=packUint2x32(uvec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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binding.U32(), ctx.var_alloc.Consume(offset));
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binding.U32(), ctx.var_alloc.Consume(offset));
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@ -182,7 +182,7 @@ void EmitStorageAtomicIAdd64(EmitContext& ctx, IR::Inst& inst, const IR::Value&
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void EmitStorageAtomicSMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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void EmitStorageAtomicSMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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const IR::Value& offset, std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 Atomics not supported, fallback to non-atomic");
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU64("{}=packInt2x32(ivec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.AddU64("{}=packInt2x32(ivec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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binding.U32(), ctx.var_alloc.Consume(offset));
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binding.U32(), ctx.var_alloc.Consume(offset));
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@ -195,7 +195,7 @@ void EmitStorageAtomicSMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value&
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void EmitStorageAtomicUMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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void EmitStorageAtomicUMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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const IR::Value& offset, std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 Atomics not supported, fallback to non-atomic");
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU64("{}=packUint2x32(uvec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.AddU64("{}=packUint2x32(uvec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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binding.U32(), ctx.var_alloc.Consume(offset));
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binding.U32(), ctx.var_alloc.Consume(offset));
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@ -207,7 +207,7 @@ void EmitStorageAtomicUMin64(EmitContext& ctx, IR::Inst& inst, const IR::Value&
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void EmitStorageAtomicSMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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void EmitStorageAtomicSMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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const IR::Value& offset, std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 Atomics not supported, fallback to non-atomic");
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU64("{}=packInt2x32(ivec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.AddU64("{}=packInt2x32(ivec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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binding.U32(), ctx.var_alloc.Consume(offset));
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binding.U32(), ctx.var_alloc.Consume(offset));
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@ -220,7 +220,7 @@ void EmitStorageAtomicSMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value&
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void EmitStorageAtomicUMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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void EmitStorageAtomicUMax64(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding,
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const IR::Value& offset, std::string_view value) {
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const IR::Value& offset, std::string_view value) {
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LOG_WARNING(Shader_GLSL, "Int64 Atomics not supported, fallback to non-atomic");
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LOG_WARNING(Shader_GLSL, "Int64 atomics not supported, fallback to non-atomic");
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ctx.AddU64("{}=packUint2x32(uvec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.AddU64("{}=packUint2x32(uvec2({}_ssbo{}[{}>>2],{}_ssbo{}[({}>>2)+1]));", inst,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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ctx.stage_name, binding.U32(), ctx.var_alloc.Consume(offset), ctx.stage_name,
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binding.U32(), ctx.var_alloc.Consume(offset));
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binding.U32(), ctx.var_alloc.Consume(offset));
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@ -17,8 +17,7 @@ void CompositeInsert(EmitContext& ctx, std::string_view result, std::string_view
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// The result is aliased with the composite
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// The result is aliased with the composite
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ctx.Add("{}.{}={};", composite, SWIZZLE[index], object);
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ctx.Add("{}.{}={};", composite, SWIZZLE[index], object);
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} else {
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} else {
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ctx.Add("{}={};", result, composite);
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ctx.Add("{}={};{}.{}={};", result, composite, result, SWIZZLE[index], object);
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ctx.Add("{}.{}={};", result, SWIZZLE[index], object);
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}
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}
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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@ -30,7 +30,7 @@ std::string InputVertexIndex(EmitContext& ctx, std::string_view vertex) {
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return IsInputArray(ctx.stage) ? fmt::format("[{}]", vertex) : "";
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return IsInputArray(ctx.stage) ? fmt::format("[{}]", vertex) : "";
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}
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}
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std::string OutputVertexIndex(EmitContext& ctx) {
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std::string_view OutputVertexIndex(EmitContext& ctx) {
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return ctx.stage == Stage::TessellationControl ? "[gl_InvocationID]" : "";
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return ctx.stage == Stage::TessellationControl ? "[gl_InvocationID]" : "";
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}
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}
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@ -40,7 +40,7 @@ void GetCbuf(EmitContext& ctx, std::string_view ret, const IR::Value& binding,
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const bool is_immediate{offset.IsImmediate()};
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const bool is_immediate{offset.IsImmediate()};
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if (is_immediate) {
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if (is_immediate) {
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const s32 signed_offset{static_cast<s32>(offset.U32())};
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const s32 signed_offset{static_cast<s32>(offset.U32())};
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static constexpr u32 cbuf_size{4096 * 16};
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static constexpr u32 cbuf_size{0x10000};
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if (signed_offset < 0 || offset.U32() > cbuf_size) {
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if (signed_offset < 0 || offset.U32() > cbuf_size) {
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LOG_WARNING(Shader_GLSL, "Immediate constant buffer offset is out of bounds");
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LOG_WARNING(Shader_GLSL, "Immediate constant buffer offset is out of bounds");
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ctx.Add("{}=0u;", ret);
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ctx.Add("{}=0u;", ret);
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@ -140,7 +140,7 @@ void EmitGetCbufU32x2(EmitContext& ctx, IR::Inst& inst, const IR::Value& binding
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const IR::Value& offset) {
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const IR::Value& offset) {
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const auto cbuf{fmt::format("{}_cbuf{}", ctx.stage_name, binding.U32())};
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const auto cbuf{fmt::format("{}_cbuf{}", ctx.stage_name, binding.U32())};
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if (offset.IsImmediate()) {
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if (offset.IsImmediate()) {
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static constexpr u32 cbuf_size{4096 * 16};
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static constexpr u32 cbuf_size{0x10000};
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const u32 u32_offset{offset.U32()};
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const u32 u32_offset{offset.U32()};
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const s32 signed_offset{static_cast<s32>(offset.U32())};
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const s32 signed_offset{static_cast<s32>(offset.U32())};
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if (signed_offset < 0 || u32_offset > cbuf_size) {
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if (signed_offset < 0 || u32_offset > cbuf_size) {
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@ -308,21 +308,13 @@ void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, std::string_view val
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case IR::Attribute::ColorFrontDiffuseG:
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case IR::Attribute::ColorFrontDiffuseG:
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case IR::Attribute::ColorFrontDiffuseB:
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case IR::Attribute::ColorFrontDiffuseB:
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case IR::Attribute::ColorFrontDiffuseA:
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case IR::Attribute::ColorFrontDiffuseA:
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if (ctx.stage == Stage::Fragment) {
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ctx.Add("gl_FrontColor.{}={};", swizzle, value);
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ctx.Add("gl_Color.{}={};", swizzle, value);
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} else {
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ctx.Add("gl_FrontColor.{}={};", swizzle, value);
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}
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break;
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break;
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case IR::Attribute::ColorFrontSpecularR:
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case IR::Attribute::ColorFrontSpecularR:
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case IR::Attribute::ColorFrontSpecularG:
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case IR::Attribute::ColorFrontSpecularG:
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case IR::Attribute::ColorFrontSpecularB:
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case IR::Attribute::ColorFrontSpecularB:
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case IR::Attribute::ColorFrontSpecularA:
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case IR::Attribute::ColorFrontSpecularA:
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if (ctx.stage == Stage::Fragment) {
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ctx.Add("gl_FrontSecondaryColor.{}={};", swizzle, value);
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ctx.Add("gl_SecondaryColor.{}={};", swizzle, value);
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} else {
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ctx.Add("gl_FrontSecondaryColor.{}={};", swizzle, value);
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}
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break;
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break;
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case IR::Attribute::ColorBackDiffuseR:
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case IR::Attribute::ColorBackDiffuseR:
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case IR::Attribute::ColorBackDiffuseG:
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case IR::Attribute::ColorBackDiffuseG:
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@ -28,6 +28,7 @@ void SetSignFlag(EmitContext& ctx, IR::Inst& inst, std::string_view result) {
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sign->Invalidate();
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sign->Invalidate();
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b) {
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void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b) {
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const auto result{ctx.var_alloc.Define(inst, GlslVarType::U32)};
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const auto result{ctx.var_alloc.Define(inst, GlslVarType::U32)};
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if (IR::Inst* const carry{inst.GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp)}) {
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if (IR::Inst* const carry{inst.GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp)}) {
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@ -20,6 +20,7 @@ void SharedWriteCas(EmitContext& ctx, std::string_view offset, std::string_view
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ctx.Add(cas_loop, smem, smem, smem, value, bit_offset, num_bits);
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ctx.Add(cas_loop, smem, smem, smem, value, bit_offset, num_bits);
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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void EmitLoadSharedU8(EmitContext& ctx, IR::Inst& inst, std::string_view offset) {
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void EmitLoadSharedU8(EmitContext& ctx, IR::Inst& inst, std::string_view offset) {
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ctx.AddU32("{}=bitfieldExtract(smem[{}>>2],int({}%4)*8,8);", inst, offset, offset);
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ctx.AddU32("{}=bitfieldExtract(smem[{}>>2],int({}%4)*8,8);", inst, offset, offset);
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}
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}
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@ -43,7 +43,7 @@ void UseShuffleNv(EmitContext& ctx, IR::Inst& inst, std::string_view shfl_op,
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ctx.AddU32("{}={}({},{},{},shfl_in_bounds);", inst, shfl_op, value, index, width);
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ctx.AddU32("{}={}({},{},{},shfl_in_bounds);", inst, shfl_op, value, index, width);
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SetInBoundsFlag(ctx, inst);
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SetInBoundsFlag(ctx, inst);
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}
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}
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} // namespace
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} // Anonymous namespace
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void EmitLaneId(EmitContext& ctx, IR::Inst& inst) {
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void EmitLaneId(EmitContext& ctx, IR::Inst& inst) {
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ctx.AddU32("{}=gl_SubGroupInvocationARB&31u;", inst);
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ctx.AddU32("{}=gl_SubGroupInvocationARB&31u;", inst);
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@ -177,8 +177,7 @@ Id VarAlloc::Alloc(GlslVarType type) {
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void VarAlloc::Free(Id id) {
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void VarAlloc::Free(Id id) {
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if (id.is_valid == 0) {
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if (id.is_valid == 0) {
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// throw LogicError("Freeing invalid variable");
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throw LogicError("Freeing invalid variable");
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return;
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}
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}
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auto& use_tracker{GetUseTracker(id.type)};
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auto& use_tracker{GetUseTracker(id.type)};
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use_tracker.var_use[id.index] = false;
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use_tracker.var_use[id.index] = false;
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@ -105,6 +105,8 @@ struct Profile {
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bool has_broken_signed_operations{};
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bool has_broken_signed_operations{};
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/// Dynamic vec4 indexing is broken on some OpenGL drivers
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/// Dynamic vec4 indexing is broken on some OpenGL drivers
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bool has_gl_component_indexing_bug{};
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bool has_gl_component_indexing_bug{};
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/// The precise type qualifier is broken in the fragment stage of some drivers
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bool has_gl_precise_bug{};
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/// Ignores SPIR-V ordered vs unordered using GLSL semantics
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/// Ignores SPIR-V ordered vs unordered using GLSL semantics
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bool ignore_nan_fp_comparisons{};
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bool ignore_nan_fp_comparisons{};
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};
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};
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@ -196,6 +196,8 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.has_broken_spirv_clamp = true,
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.has_broken_spirv_clamp = true,
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.has_broken_unsigned_image_offsets = true,
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.has_broken_unsigned_image_offsets = true,
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.has_broken_signed_operations = true,
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.has_broken_signed_operations = true,
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.has_gl_component_indexing_bug = device.HasComponentIndexingBug(),
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.has_gl_precise_bug = device.HasPreciseBug(),
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.ignore_nan_fp_comparisons = true,
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.ignore_nan_fp_comparisons = true,
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} {
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} {
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if (use_asynchronous_shaders) {
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if (use_asynchronous_shaders) {
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