mirror of
https://github.com/yuzu-mirror/yuzu
synced 2024-12-01 03:29:08 +00:00
Pica/CommandProcessor: Properly implement shader load destination offset registers.
This commit is contained in:
parent
67120270f2
commit
6c26ec72a5
2 changed files with 10 additions and 20 deletions
|
@ -25,10 +25,6 @@ static int float_regs_counter = 0;
|
|||
|
||||
static u32 uniform_write_buffer[4];
|
||||
|
||||
// Used for VSLoadProgramData and VSLoadSwizzleData
|
||||
static u32 vs_binary_write_offset = 0;
|
||||
static u32 vs_swizzle_write_offset = 0;
|
||||
|
||||
static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
|
||||
|
||||
if (id >= registers.NumIds())
|
||||
|
@ -258,11 +254,6 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
|
|||
break;
|
||||
}
|
||||
|
||||
// Seems to be used to reset the write pointer for VSLoadProgramData
|
||||
case PICA_REG_INDEX(vs_program.begin_load):
|
||||
vs_binary_write_offset = 0;
|
||||
break;
|
||||
|
||||
// Load shader program code
|
||||
case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
|
||||
case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
|
||||
|
@ -273,16 +264,11 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
|
|||
case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[6], 0x2d2):
|
||||
case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[7], 0x2d3):
|
||||
{
|
||||
VertexShader::SubmitShaderMemoryChange(vs_binary_write_offset, value);
|
||||
vs_binary_write_offset++;
|
||||
VertexShader::SubmitShaderMemoryChange(registers.vs_program.offset, value);
|
||||
registers.vs_program.offset++;
|
||||
break;
|
||||
}
|
||||
|
||||
// Seems to be used to reset the write pointer for VSLoadSwizzleData
|
||||
case PICA_REG_INDEX(vs_swizzle_patterns.begin_load):
|
||||
vs_swizzle_write_offset = 0;
|
||||
break;
|
||||
|
||||
// Load swizzle pattern data
|
||||
case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[0], 0x2d6):
|
||||
case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[1], 0x2d7):
|
||||
|
@ -293,8 +279,8 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
|
|||
case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[6], 0x2dc):
|
||||
case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[7], 0x2dd):
|
||||
{
|
||||
VertexShader::SubmitSwizzleDataChange(vs_swizzle_write_offset, value);
|
||||
vs_swizzle_write_offset++;
|
||||
VertexShader::SubmitSwizzleDataChange(registers.vs_swizzle_patterns.offset, value);
|
||||
registers.vs_swizzle_patterns.offset++;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -678,7 +678,9 @@ struct Regs {
|
|||
INSERT_PADDING_WORDS(0x2);
|
||||
|
||||
struct {
|
||||
u32 begin_load;
|
||||
// Offset of the next instruction to write code to.
|
||||
// Incremented with each instruction write.
|
||||
u32 offset;
|
||||
|
||||
// Writing to these registers sets the "current" word in the shader program.
|
||||
// TODO: It's not clear how the hardware stores what the "current" word is.
|
||||
|
@ -690,7 +692,9 @@ struct Regs {
|
|||
// This register group is used to load an internal table of swizzling patterns,
|
||||
// which are indexed by each shader instruction to specify vector component swizzling.
|
||||
struct {
|
||||
u32 begin_load;
|
||||
// Offset of the next swizzle pattern to write code to.
|
||||
// Incremented with each instruction write.
|
||||
u32 offset;
|
||||
|
||||
// Writing to these registers sets the "current" swizzle pattern in the table.
|
||||
// TODO: It's not clear how the hardware stores what the "current" swizzle pattern is.
|
||||
|
|
Loading…
Reference in a new issue