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Vulkan: Implement Alpha coverage
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a52d0b82a6
commit
6352c5dc31
3 changed files with 6 additions and 2 deletions
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@ -93,6 +93,8 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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provoking_vertex_last.Assign(regs.provoking_vertex == Maxwell::ProvokingVertex::Last ? 1 : 0);
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provoking_vertex_last.Assign(regs.provoking_vertex == Maxwell::ProvokingVertex::Last ? 1 : 0);
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conservative_raster_enable.Assign(regs.conservative_raster_enable != 0 ? 1 : 0);
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conservative_raster_enable.Assign(regs.conservative_raster_enable != 0 ? 1 : 0);
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smooth_lines.Assign(regs.line_anti_alias_enable != 0 ? 1 : 0);
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smooth_lines.Assign(regs.line_anti_alias_enable != 0 ? 1 : 0);
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alpha_to_coverage_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_coverage != 0 ? 1 : 0);
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alpha_to_one_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_one != 0 ? 1 : 0);
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for (size_t i = 0; i < regs.rt.size(); ++i) {
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for (size_t i = 0; i < regs.rt.size(); ++i) {
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color_formats[i] = static_cast<u8>(regs.rt[i].format);
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color_formats[i] = static_cast<u8>(regs.rt[i].format);
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@ -195,6 +195,8 @@ struct FixedPipelineState {
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BitField<12, 1, u32> provoking_vertex_last;
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BitField<12, 1, u32> provoking_vertex_last;
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BitField<13, 1, u32> conservative_raster_enable;
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BitField<13, 1, u32> conservative_raster_enable;
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BitField<14, 1, u32> smooth_lines;
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BitField<14, 1, u32> smooth_lines;
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BitField<15, 1, u32> alpha_to_coverage_enabled;
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BitField<16, 1, u32> alpha_to_one_enabled;
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};
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};
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std::array<u8, Maxwell::NumRenderTargets> color_formats;
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std::array<u8, Maxwell::NumRenderTargets> color_formats;
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@ -714,8 +714,8 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.sampleShadingEnable = VK_FALSE,
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.sampleShadingEnable = VK_FALSE,
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.minSampleShading = 0.0f,
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.minSampleShading = 0.0f,
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.pSampleMask = nullptr,
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.pSampleMask = nullptr,
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.alphaToCoverageEnable = VK_FALSE,
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.alphaToCoverageEnable = key.state.alpha_to_coverage_enabled != 0 ? VK_TRUE : VK_FALSE,
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.alphaToOneEnable = VK_FALSE,
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.alphaToOneEnable = key.state.alpha_to_one_enabled != 0 ? VK_TRUE : VK_FALSE,
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};
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};
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const VkPipelineDepthStencilStateCreateInfo depth_stencil_ci{
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const VkPipelineDepthStencilStateCreateInfo depth_stencil_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
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