Mirrors/yuzu
2
0
Fork 0
mirror of https://github.com/yuzu-mirror/yuzu synced 2024-12-24 20:23:05 +00:00
Code Issues Projects Releases Packages Wiki Activity

glasm: Add logical instructions on GLASM

Browse source
This commit is contained in:
ReinUsesLisp 2021-05-09 21:17:48 -03:00 committed by ameerj
parent 99352741af
commit 43a448d98d
2 changed files with 12 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/shader_recompiler/backend/glasm/emit_glasm_instructions.h
View file

@ -437,10 +437,10 @@ void EmitGlobalAtomicMinF16x2(EmitContext& ctx);
void EmitGlobalAtomicMinF32x2(EmitContext& ctx); void EmitGlobalAtomicMinF32x2(EmitContext& ctx);
void EmitGlobalAtomicMaxF16x2(EmitContext& ctx); void EmitGlobalAtomicMaxF16x2(EmitContext& ctx);
void EmitGlobalAtomicMaxF32x2(EmitContext& ctx); void EmitGlobalAtomicMaxF32x2(EmitContext& ctx);
void EmitLogicalOr(EmitContext& ctx, ScalarS32 a, ScalarS32 b); void EmitLogicalOr(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
void EmitLogicalAnd(EmitContext& ctx, ScalarS32 a, ScalarS32 b); void EmitLogicalAnd(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
void EmitLogicalXor(EmitContext& ctx, ScalarS32 a, ScalarS32 b); void EmitLogicalXor(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
void EmitLogicalNot(EmitContext& ctx, ScalarS32 value); void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
void EmitConvertS16F16(EmitContext& ctx, Register value); void EmitConvertS16F16(EmitContext& ctx, Register value);
void EmitConvertS16F32(EmitContext& ctx, Register value); void EmitConvertS16F32(EmitContext& ctx, Register value);
void EmitConvertS16F64(EmitContext& ctx, Register value); void EmitConvertS16F64(EmitContext& ctx, Register value);

16
src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp
View file

@ -572,20 +572,20 @@ void EmitGlobalAtomicMaxF32x2(EmitContext& ctx) {
NotImplemented(); NotImplemented();
} }
void EmitLogicalOr(EmitContext& ctx, ScalarS32 a, ScalarS32 b) { void EmitLogicalOr(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
NotImplemented(); ctx.Add("OR.S {},{},{};", inst, a, b);
} }
void EmitLogicalAnd(EmitContext& ctx, ScalarS32 a, ScalarS32 b) { void EmitLogicalAnd(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
NotImplemented(); ctx.Add("AND.S {},{},{};", inst, a, b);
} }
void EmitLogicalXor(EmitContext& ctx, ScalarS32 a, ScalarS32 b) { void EmitLogicalXor(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
NotImplemented(); ctx.Add("XOR.S {},{},{};", inst, a, b);
} }
void EmitLogicalNot(EmitContext& ctx, ScalarS32 value) { void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
NotImplemented(); ctx.Add("SEQ.S {},{},0;", inst, value);
} }
void EmitConvertS16F16(EmitContext& ctx, Register value) { void EmitConvertS16F16(EmitContext& ctx, Register value) {