Mirrors/yuzu
2
0
Fork 0
mirror of https://github.com/yuzu-mirror/yuzu synced 2024-12-20 05:33:09 +00:00
Code Issues Projects Releases Packages Wiki Activity

glasm: Use BitField instead of C bitfields

Browse source
This commit is contained in:
ReinUsesLisp 2021-05-08 16:46:32 -03:00 committed by ameerj
parent 2b04b4d27f
commit 3e841f6441
2 changed files with 12 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/shader_recompiler/backend/glasm/reg_alloc.cpp
View file

@ -68,11 +68,11 @@ Id RegAlloc::Alloc() {
} }
num_used_registers = std::max(num_used_registers, reg + 1); num_used_registers = std::max(num_used_registers, reg + 1);
register_use[reg] = true; register_use[reg] = true;
return Id{ Id ret{};
.index = static_cast<u32>(reg), ret.index.Assign(static_cast<u32>(reg));
.is_spill = 0, ret.is_spill.Assign(0);
.is_condition_code = 0, ret.is_condition_code.Assign(0);
}; return ret;
} }
throw NotImplementedException("Register spilling"); throw NotImplementedException("Register spilling");
} }

10
src/shader_recompiler/backend/glasm/reg_alloc.h
View file

@ -6,6 +6,7 @@
#include <bitset> #include <bitset>
#include "common/bit_field.h"
#include "common/common_types.h" #include "common/common_types.h"
namespace Shader::IR { namespace Shader::IR {
@ -18,9 +19,12 @@ namespace Shader::Backend::GLASM {
class EmitContext; class EmitContext;
struct Id { struct Id {
u32 index : 30; union {
u32 is_spill : 1; u32 raw;
u32 is_condition_code : 1; BitField<0, 30, u32> index;
BitField<30, 1, u32> is_spill;
BitField<31, 1, u32> is_condition_code;
};
}; };
class RegAlloc { class RegAlloc {