mirror of
https://github.com/yuzu-mirror/yuzu
synced 2024-12-23 22:43:04 +00:00
shader: Implement BFI
This commit is contained in:
parent
34ac9b4d7e
commit
08a9e95905
3 changed files with 57 additions and 16 deletions
|
@ -60,6 +60,7 @@ add_library(shader_recompiler STATIC
|
|||
frontend/maxwell/program.cpp
|
||||
frontend/maxwell/program.h
|
||||
frontend/maxwell/translate/impl/bitfield_extract.cpp
|
||||
frontend/maxwell/translate/impl/bitfield_insert.cpp
|
||||
frontend/maxwell/translate/impl/common_encoding.h
|
||||
frontend/maxwell/translate/impl/floating_point_add.cpp
|
||||
frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
|
||||
|
|
|
@ -0,0 +1,56 @@
|
|||
// Copyright 2021 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_types.h"
|
||||
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
|
||||
|
||||
namespace Shader::Maxwell {
|
||||
namespace {
|
||||
void BFI(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::U32& base) {
|
||||
union {
|
||||
u64 insn;
|
||||
BitField<0, 8, IR::Reg> dest_reg;
|
||||
BitField<8, 8, IR::Reg> insert_reg;
|
||||
} const bfi{insn};
|
||||
|
||||
const IR::U32 offset{v.ir.BitFieldExtract(src_a, v.ir.Imm32(0), v.ir.Imm32(8), false)};
|
||||
const IR::U32 unsafe_count{v.ir.BitFieldExtract(src_a, v.ir.Imm32(8), v.ir.Imm32(8), false)};
|
||||
const IR::U32 max_size{v.ir.Imm32(32)};
|
||||
|
||||
// Edge case conditions
|
||||
const IR::U1 zero_offset{v.ir.IEqual(offset, v.ir.Imm32(0))};
|
||||
const IR::U1 exceed_offset{v.ir.IGreaterThanEqual(offset, max_size, false)};
|
||||
const IR::U1 exceed_count{v.ir.IGreaterThanEqual(unsafe_count, max_size, false)};
|
||||
|
||||
const IR::U32 remaining_size{v.ir.ISub(max_size, offset)};
|
||||
const IR::U32 safe_count{v.ir.Select(exceed_count, remaining_size, unsafe_count)};
|
||||
|
||||
const IR::U32 insert{v.X(bfi.insert_reg)};
|
||||
IR::U32 result{v.ir.BitFieldInsert(base, insert, offset, safe_count)};
|
||||
|
||||
result = IR::U32{v.ir.Select(exceed_offset, base, result)};
|
||||
result = IR::U32{v.ir.Select(zero_offset, base, result)};
|
||||
|
||||
v.X(bfi.dest_reg, result);
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
void TranslatorVisitor::BFI_reg(u64 insn) {
|
||||
BFI(*this, insn, GetReg20(insn), GetReg39(insn));
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_rc(u64 insn) {
|
||||
BFI(*this, insn, GetReg39(insn), GetCbuf(insn));
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_cr(u64 insn) {
|
||||
BFI(*this, insn, GetCbuf(insn), GetReg39(insn));
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_imm(u64 insn) {
|
||||
BFI(*this, insn, GetImm20(insn), GetReg39(insn));
|
||||
}
|
||||
|
||||
} // namespace Shader::Maxwell
|
|
@ -49,22 +49,6 @@ void TranslatorVisitor::BAR(u64) {
|
|||
ThrowNotImplemented(Opcode::BAR);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_reg(u64) {
|
||||
ThrowNotImplemented(Opcode::BFI_reg);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_rc(u64) {
|
||||
ThrowNotImplemented(Opcode::BFI_rc);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_cr(u64) {
|
||||
ThrowNotImplemented(Opcode::BFI_cr);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BFI_imm(u64) {
|
||||
ThrowNotImplemented(Opcode::BFI_imm);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::BPT(u64) {
|
||||
ThrowNotImplemented(Opcode::BPT);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue