mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-12-24 11:43:09 +00:00
acc39a4bc0
* Api Symbols: replace asserts with checks * Api Symbols: replace asserts with checks part 2 * Update no args function signatures with void, to help compiler to track incorrect usage * More unavoidable void * Update PVS config and code to make it happy * Format sources * nfc: fix checks * dead code cleanup & include fixes Co-authored-by: gornekich <n.gorbadey@gmail.com> Co-authored-by: hedger <hedger@users.noreply.github.com> Co-authored-by: hedger <hedger@nanode.su>
621 lines
21 KiB
C
621 lines
21 KiB
C
#include "furi_hal_nfc_i.h"
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#include "furi_hal_nfc_tech_i.h"
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#include <lib/drivers/st25r3916.h>
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#include <furi.h>
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#include <furi_hal_spi.h>
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#define TAG "FuriHalNfc"
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const FuriHalNfcTechBase* furi_hal_nfc_tech[FuriHalNfcTechNum] = {
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[FuriHalNfcTechIso14443a] = &furi_hal_nfc_iso14443a,
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[FuriHalNfcTechIso14443b] = &furi_hal_nfc_iso14443b,
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[FuriHalNfcTechIso15693] = &furi_hal_nfc_iso15693,
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[FuriHalNfcTechFelica] = &furi_hal_nfc_felica,
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// Add new technologies here
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};
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FuriHalNfc furi_hal_nfc;
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static FuriHalNfcError furi_hal_nfc_turn_on_osc(FuriHalSpiBusHandle* handle) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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furi_hal_nfc_event_start();
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if(!st25r3916_check_reg(
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handle,
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ST25R3916_REG_OP_CONTROL,
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ST25R3916_REG_OP_CONTROL_en,
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ST25R3916_REG_OP_CONTROL_en)) {
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st25r3916_mask_irq(handle, ~ST25R3916_IRQ_MASK_OSC);
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st25r3916_set_reg_bits(handle, ST25R3916_REG_OP_CONTROL, ST25R3916_REG_OP_CONTROL_en);
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furi_hal_nfc_event_wait_for_specific_irq(handle, ST25R3916_IRQ_MASK_OSC, 10);
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}
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// Disable IRQs
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st25r3916_mask_irq(handle, ST25R3916_IRQ_MASK_ALL);
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bool osc_on = st25r3916_check_reg(
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handle,
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ST25R3916_REG_AUX_DISPLAY,
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ST25R3916_REG_AUX_DISPLAY_osc_ok,
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ST25R3916_REG_AUX_DISPLAY_osc_ok);
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if(!osc_on) {
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error = FuriHalNfcErrorOscillator;
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}
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return error;
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}
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FuriHalNfcError furi_hal_nfc_is_hal_ready(void) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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do {
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error = furi_hal_nfc_acquire();
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if(error != FuriHalNfcErrorNone) break;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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uint8_t chip_id = 0;
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st25r3916_read_reg(handle, ST25R3916_REG_IC_IDENTITY, &chip_id);
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if((chip_id & ST25R3916_REG_IC_IDENTITY_ic_type_mask) !=
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ST25R3916_REG_IC_IDENTITY_ic_type_st25r3916) {
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FURI_LOG_E(TAG, "Wrong chip id");
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error = FuriHalNfcErrorCommunication;
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}
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furi_hal_nfc_release();
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} while(false);
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return error;
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}
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FuriHalNfcError furi_hal_nfc_init(void) {
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furi_check(furi_hal_nfc.mutex == NULL);
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furi_hal_nfc.mutex = furi_mutex_alloc(FuriMutexTypeNormal);
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FuriHalNfcError error = FuriHalNfcErrorNone;
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furi_hal_nfc_event_init();
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furi_hal_nfc_event_start();
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do {
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error = furi_hal_nfc_acquire();
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if(error != FuriHalNfcErrorNone) {
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furi_hal_nfc_low_power_mode_start();
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}
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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// Set default state
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st25r3916_direct_cmd(handle, ST25R3916_CMD_SET_DEFAULT);
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// Increase IO driver strength of MISO and IRQ
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st25r3916_write_reg(handle, ST25R3916_REG_IO_CONF2, ST25R3916_REG_IO_CONF2_io_drv_lvl);
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// Check chip ID
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uint8_t chip_id = 0;
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st25r3916_read_reg(handle, ST25R3916_REG_IC_IDENTITY, &chip_id);
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if((chip_id & ST25R3916_REG_IC_IDENTITY_ic_type_mask) !=
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ST25R3916_REG_IC_IDENTITY_ic_type_st25r3916) {
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FURI_LOG_E(TAG, "Wrong chip id");
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error = FuriHalNfcErrorCommunication;
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furi_hal_nfc_low_power_mode_start();
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furi_hal_nfc_release();
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break;
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}
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// Clear interrupts
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st25r3916_get_irq(handle);
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// Mask all interrupts
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st25r3916_mask_irq(handle, ST25R3916_IRQ_MASK_ALL);
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// Enable interrupts
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furi_hal_nfc_init_gpio_isr();
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// Disable internal overheat protection
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st25r3916_change_test_reg_bits(handle, 0x04, 0x10, 0x10);
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error = furi_hal_nfc_turn_on_osc(handle);
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if(error != FuriHalNfcErrorNone) {
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furi_hal_nfc_low_power_mode_start();
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furi_hal_nfc_release();
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break;
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}
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// Measure voltage
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// Set measure power supply voltage source
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_REGULATOR_CONTROL,
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ST25R3916_REG_REGULATOR_CONTROL_mpsv_mask,
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ST25R3916_REG_REGULATOR_CONTROL_mpsv_vdd);
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// Enable timer and interrupt register
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st25r3916_mask_irq(handle, ~ST25R3916_IRQ_MASK_DCT);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_MEASURE_VDD);
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furi_hal_nfc_event_wait_for_specific_irq(handle, ST25R3916_IRQ_MASK_DCT, 100);
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st25r3916_mask_irq(handle, ST25R3916_IRQ_MASK_ALL);
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uint8_t ad_res = 0;
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st25r3916_read_reg(handle, ST25R3916_REG_AD_RESULT, &ad_res);
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uint16_t mV = ((uint16_t)ad_res) * 23U;
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mV += (((((uint16_t)ad_res) * 4U) + 5U) / 10U);
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if(mV < 3600) {
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_IO_CONF2,
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ST25R3916_REG_IO_CONF2_sup3V,
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ST25R3916_REG_IO_CONF2_sup3V_3V);
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} else {
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_IO_CONF2,
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ST25R3916_REG_IO_CONF2_sup3V,
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ST25R3916_REG_IO_CONF2_sup3V_5V);
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}
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// Disable MCU CLK
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_IO_CONF1,
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ST25R3916_REG_IO_CONF1_out_cl_mask | ST25R3916_REG_IO_CONF1_lf_clk_off,
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0x07);
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// Disable MISO pull-down
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_IO_CONF2,
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ST25R3916_REG_IO_CONF2_miso_pd1 | ST25R3916_REG_IO_CONF2_miso_pd2,
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0x00);
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// Set tx driver resistance to 1 Om
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st25r3916_change_reg_bits(
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handle, ST25R3916_REG_TX_DRIVER, ST25R3916_REG_TX_DRIVER_d_res_mask, 0x00);
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// Use minimum non-overlap
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_RES_AM_MOD,
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ST25R3916_REG_RES_AM_MOD_fa3_f,
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ST25R3916_REG_RES_AM_MOD_fa3_f);
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// Set activation threashold
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_FIELD_THRESHOLD_ACTV,
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ST25R3916_REG_FIELD_THRESHOLD_ACTV_trg_mask,
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ST25R3916_REG_FIELD_THRESHOLD_ACTV_trg_105mV);
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_FIELD_THRESHOLD_ACTV,
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ST25R3916_REG_FIELD_THRESHOLD_ACTV_rfe_mask,
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ST25R3916_REG_FIELD_THRESHOLD_ACTV_rfe_105mV);
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// Set deactivation threashold
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_FIELD_THRESHOLD_DEACTV,
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ST25R3916_REG_FIELD_THRESHOLD_DEACTV_trg_mask,
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ST25R3916_REG_FIELD_THRESHOLD_DEACTV_trg_75mV);
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_FIELD_THRESHOLD_DEACTV,
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ST25R3916_REG_FIELD_THRESHOLD_DEACTV_rfe_mask,
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ST25R3916_REG_FIELD_THRESHOLD_DEACTV_rfe_75mV);
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// Enable external load modulation
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_AUX_MOD,
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ST25R3916_REG_AUX_MOD_lm_ext,
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ST25R3916_REG_AUX_MOD_lm_ext);
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// Enable internal load modulation
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_AUX_MOD,
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ST25R3916_REG_AUX_MOD_lm_dri,
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ST25R3916_REG_AUX_MOD_lm_dri);
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// Adjust FDT
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_PASSIVE_TARGET,
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ST25R3916_REG_PASSIVE_TARGET_fdel_mask,
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(5U << ST25R3916_REG_PASSIVE_TARGET_fdel_shift));
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// Reduce RFO resistance in Modulated state
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_PT_MOD,
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ST25R3916_REG_PT_MOD_ptm_res_mask | ST25R3916_REG_PT_MOD_pt_res_mask,
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0x0f);
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// Enable RX start on first 4 bits
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_EMD_SUP_CONF,
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ST25R3916_REG_EMD_SUP_CONF_rx_start_emv,
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ST25R3916_REG_EMD_SUP_CONF_rx_start_emv_on);
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// Set antena tunning
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st25r3916_change_reg_bits(handle, ST25R3916_REG_ANT_TUNE_A, 0xff, 0x82);
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st25r3916_change_reg_bits(handle, ST25R3916_REG_ANT_TUNE_B, 0xff, 0x82);
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_OP_CONTROL,
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ST25R3916_REG_OP_CONTROL_en_fd_mask,
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ST25R3916_REG_OP_CONTROL_en_fd_auto_efd);
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// Perform calibration
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if(st25r3916_check_reg(
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handle,
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ST25R3916_REG_REGULATOR_CONTROL,
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ST25R3916_REG_REGULATOR_CONTROL_reg_s,
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0x00)) {
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FURI_LOG_I(TAG, "Adjusting regulators");
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// Reset logic
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st25r3916_set_reg_bits(
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handle, ST25R3916_REG_REGULATOR_CONTROL, ST25R3916_REG_REGULATOR_CONTROL_reg_s);
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st25r3916_clear_reg_bits(
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handle, ST25R3916_REG_REGULATOR_CONTROL, ST25R3916_REG_REGULATOR_CONTROL_reg_s);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_ADJUST_REGULATORS);
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furi_delay_ms(6);
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}
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furi_hal_nfc_low_power_mode_start();
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furi_hal_nfc_release();
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} while(false);
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return error;
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}
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static bool furi_hal_nfc_is_mine(void) {
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return (furi_mutex_get_owner(furi_hal_nfc.mutex) == furi_thread_get_current_id());
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}
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FuriHalNfcError furi_hal_nfc_acquire(void) {
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furi_check(furi_hal_nfc.mutex);
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_nfc);
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FuriHalNfcError error = FuriHalNfcErrorNone;
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if(furi_mutex_acquire(furi_hal_nfc.mutex, 100) != FuriStatusOk) {
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furi_hal_spi_release(&furi_hal_spi_bus_handle_nfc);
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error = FuriHalNfcErrorBusy;
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}
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return error;
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}
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FuriHalNfcError furi_hal_nfc_release(void) {
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furi_check(furi_hal_nfc.mutex);
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furi_check(furi_hal_nfc_is_mine());
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furi_check(furi_mutex_release(furi_hal_nfc.mutex) == FuriStatusOk);
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furi_hal_spi_release(&furi_hal_spi_bus_handle_nfc);
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return FuriHalNfcErrorNone;
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}
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FuriHalNfcError furi_hal_nfc_low_power_mode_start(void) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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st25r3916_direct_cmd(handle, ST25R3916_CMD_STOP);
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st25r3916_clear_reg_bits(
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handle,
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ST25R3916_REG_OP_CONTROL,
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(ST25R3916_REG_OP_CONTROL_en | ST25R3916_REG_OP_CONTROL_rx_en |
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ST25R3916_REG_OP_CONTROL_wu | ST25R3916_REG_OP_CONTROL_tx_en |
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ST25R3916_REG_OP_CONTROL_en_fd_mask));
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furi_hal_nfc_deinit_gpio_isr();
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furi_hal_nfc_timers_deinit();
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furi_hal_nfc_event_stop();
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return error;
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}
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FuriHalNfcError furi_hal_nfc_low_power_mode_stop(void) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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do {
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furi_hal_nfc_init_gpio_isr();
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furi_hal_nfc_timers_init();
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error = furi_hal_nfc_turn_on_osc(handle);
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if(error != FuriHalNfcErrorNone) break;
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_OP_CONTROL,
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ST25R3916_REG_OP_CONTROL_en_fd_mask,
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ST25R3916_REG_OP_CONTROL_en_fd_auto_efd);
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} while(false);
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return error;
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}
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static FuriHalNfcError furi_hal_nfc_poller_init_common(FuriHalSpiBusHandle* handle) {
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// Disable wake up
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st25r3916_clear_reg_bits(handle, ST25R3916_REG_OP_CONTROL, ST25R3916_REG_OP_CONTROL_wu);
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// Enable correlator
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_AUX,
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ST25R3916_REG_AUX_dis_corr,
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ST25R3916_REG_AUX_dis_corr_correlator);
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st25r3916_change_reg_bits(handle, ST25R3916_REG_ANT_TUNE_A, 0xff, 0x82);
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st25r3916_change_reg_bits(handle, ST25R3916_REG_ANT_TUNE_B, 0xFF, 0x82);
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st25r3916_write_reg(handle, ST25R3916_REG_OVERSHOOT_CONF1, 0x00);
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st25r3916_write_reg(handle, ST25R3916_REG_OVERSHOOT_CONF2, 0x00);
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st25r3916_write_reg(handle, ST25R3916_REG_UNDERSHOOT_CONF1, 0x00);
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st25r3916_write_reg(handle, ST25R3916_REG_UNDERSHOOT_CONF2, 0x00);
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return FuriHalNfcErrorNone;
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}
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static FuriHalNfcError furi_hal_nfc_listener_init_common(FuriHalSpiBusHandle* handle) {
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UNUSED(handle);
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// No common listener configuration
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return FuriHalNfcErrorNone;
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}
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FuriHalNfcError furi_hal_nfc_set_mode(FuriHalNfcMode mode, FuriHalNfcTech tech) {
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furi_check(mode < FuriHalNfcModeNum);
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furi_check(tech < FuriHalNfcTechNum);
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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FuriHalNfcError error = FuriHalNfcErrorNone;
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if(mode == FuriHalNfcModePoller) {
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do {
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error = furi_hal_nfc_poller_init_common(handle);
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if(error != FuriHalNfcErrorNone) break;
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error = furi_hal_nfc_tech[tech]->poller.init(handle);
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} while(false);
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} else if(mode == FuriHalNfcModeListener) {
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do {
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error = furi_hal_nfc_listener_init_common(handle);
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if(error != FuriHalNfcErrorNone) break;
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error = furi_hal_nfc_tech[tech]->listener.init(handle);
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} while(false);
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}
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furi_hal_nfc.mode = mode;
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furi_hal_nfc.tech = tech;
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return error;
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}
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FuriHalNfcError furi_hal_nfc_reset_mode(void) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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st25r3916_direct_cmd(handle, ST25R3916_CMD_STOP);
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const FuriHalNfcMode mode = furi_hal_nfc.mode;
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const FuriHalNfcTech tech = furi_hal_nfc.tech;
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if(mode == FuriHalNfcModePoller) {
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error = furi_hal_nfc_tech[tech]->poller.deinit(handle);
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} else if(mode == FuriHalNfcModeListener) {
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error = furi_hal_nfc_tech[tech]->listener.deinit(handle);
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}
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// Set default value in mode register
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st25r3916_write_reg(handle, ST25R3916_REG_MODE, ST25R3916_REG_MODE_om0);
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st25r3916_write_reg(handle, ST25R3916_REG_STREAM_MODE, 0);
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st25r3916_clear_reg_bits(handle, ST25R3916_REG_AUX, ST25R3916_REG_AUX_no_crc_rx);
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st25r3916_clear_reg_bits(
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handle,
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ST25R3916_REG_BIT_RATE,
|
|
ST25R3916_REG_BIT_RATE_txrate_mask | ST25R3916_REG_BIT_RATE_rxrate_mask);
|
|
|
|
// Write default values
|
|
st25r3916_write_reg(handle, ST25R3916_REG_RX_CONF1, 0);
|
|
st25r3916_write_reg(
|
|
handle,
|
|
ST25R3916_REG_RX_CONF2,
|
|
ST25R3916_REG_RX_CONF2_sqm_dyn | ST25R3916_REG_RX_CONF2_agc_en |
|
|
ST25R3916_REG_RX_CONF2_agc_m);
|
|
|
|
st25r3916_write_reg(
|
|
handle,
|
|
ST25R3916_REG_CORR_CONF1,
|
|
ST25R3916_REG_CORR_CONF1_corr_s7 | ST25R3916_REG_CORR_CONF1_corr_s4 |
|
|
ST25R3916_REG_CORR_CONF1_corr_s1 | ST25R3916_REG_CORR_CONF1_corr_s0);
|
|
st25r3916_write_reg(handle, ST25R3916_REG_CORR_CONF2, 0);
|
|
|
|
return error;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_field_detect_start(void) {
|
|
FuriHalNfcError error = FuriHalNfcErrorNone;
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
st25r3916_write_reg(
|
|
handle,
|
|
ST25R3916_REG_OP_CONTROL,
|
|
ST25R3916_REG_OP_CONTROL_en | ST25R3916_REG_OP_CONTROL_en_fd_mask);
|
|
st25r3916_write_reg(
|
|
handle, ST25R3916_REG_MODE, ST25R3916_REG_MODE_targ | ST25R3916_REG_MODE_om0);
|
|
|
|
return error;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_field_detect_stop(void) {
|
|
FuriHalNfcError error = FuriHalNfcErrorNone;
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
st25r3916_clear_reg_bits(
|
|
handle,
|
|
ST25R3916_REG_OP_CONTROL,
|
|
(ST25R3916_REG_OP_CONTROL_en | ST25R3916_REG_OP_CONTROL_en_fd_mask));
|
|
|
|
return error;
|
|
}
|
|
|
|
bool furi_hal_nfc_field_is_present(void) {
|
|
bool is_present = false;
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
if(st25r3916_check_reg(
|
|
handle,
|
|
ST25R3916_REG_AUX_DISPLAY,
|
|
ST25R3916_REG_AUX_DISPLAY_efd_o,
|
|
ST25R3916_REG_AUX_DISPLAY_efd_o)) {
|
|
is_present = true;
|
|
}
|
|
|
|
return is_present;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_poller_field_on(void) {
|
|
FuriHalNfcError error = FuriHalNfcErrorNone;
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
if(!st25r3916_check_reg(
|
|
handle,
|
|
ST25R3916_REG_OP_CONTROL,
|
|
ST25R3916_REG_OP_CONTROL_tx_en,
|
|
ST25R3916_REG_OP_CONTROL_tx_en)) {
|
|
// Set min guard time
|
|
st25r3916_write_reg(handle, ST25R3916_REG_FIELD_ON_GT, 0);
|
|
// Enable tx rx
|
|
st25r3916_set_reg_bits(
|
|
handle,
|
|
ST25R3916_REG_OP_CONTROL,
|
|
(ST25R3916_REG_OP_CONTROL_rx_en | ST25R3916_REG_OP_CONTROL_tx_en));
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_poller_tx_common(
|
|
FuriHalSpiBusHandle* handle,
|
|
const uint8_t* tx_data,
|
|
size_t tx_bits) {
|
|
furi_check(tx_data);
|
|
|
|
FuriHalNfcError err = FuriHalNfcErrorNone;
|
|
|
|
// Prepare tx
|
|
st25r3916_direct_cmd(handle, ST25R3916_CMD_CLEAR_FIFO);
|
|
st25r3916_clear_reg_bits(
|
|
handle, ST25R3916_REG_TIMER_EMV_CONTROL, ST25R3916_REG_TIMER_EMV_CONTROL_nrt_emv);
|
|
st25r3916_change_reg_bits(
|
|
handle,
|
|
ST25R3916_REG_ISO14443A_NFC,
|
|
(ST25R3916_REG_ISO14443A_NFC_no_tx_par | ST25R3916_REG_ISO14443A_NFC_no_rx_par),
|
|
(ST25R3916_REG_ISO14443A_NFC_no_tx_par_off | ST25R3916_REG_ISO14443A_NFC_no_rx_par_off));
|
|
uint32_t interrupts =
|
|
(ST25R3916_IRQ_MASK_FWL | ST25R3916_IRQ_MASK_TXE | ST25R3916_IRQ_MASK_RXS |
|
|
ST25R3916_IRQ_MASK_RXE | ST25R3916_IRQ_MASK_PAR | ST25R3916_IRQ_MASK_CRC |
|
|
ST25R3916_IRQ_MASK_ERR1 | ST25R3916_IRQ_MASK_ERR2 | ST25R3916_IRQ_MASK_NRE);
|
|
// Clear interrupts
|
|
st25r3916_get_irq(handle);
|
|
// Enable interrupts
|
|
st25r3916_mask_irq(handle, ~interrupts);
|
|
|
|
st25r3916_write_fifo(handle, tx_data, tx_bits);
|
|
st25r3916_direct_cmd(handle, ST25R3916_CMD_TRANSMIT_WITHOUT_CRC);
|
|
|
|
return err;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_common_fifo_tx(
|
|
FuriHalSpiBusHandle* handle,
|
|
const uint8_t* tx_data,
|
|
size_t tx_bits) {
|
|
FuriHalNfcError err = FuriHalNfcErrorNone;
|
|
|
|
st25r3916_direct_cmd(handle, ST25R3916_CMD_CLEAR_FIFO);
|
|
st25r3916_write_fifo(handle, tx_data, tx_bits);
|
|
st25r3916_direct_cmd(handle, ST25R3916_CMD_TRANSMIT_WITHOUT_CRC);
|
|
|
|
return err;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_poller_tx(const uint8_t* tx_data, size_t tx_bits) {
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModePoller);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->poller.tx(handle, tx_data, tx_bits);
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_poller_rx(uint8_t* rx_data, size_t rx_data_size, size_t* rx_bits) {
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModePoller);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->poller.rx(handle, rx_data, rx_data_size, rx_bits);
|
|
}
|
|
|
|
FuriHalNfcEvent furi_hal_nfc_poller_wait_event(uint32_t timeout_ms) {
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModePoller);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->poller.wait_event(timeout_ms);
|
|
}
|
|
|
|
FuriHalNfcEvent furi_hal_nfc_listener_wait_event(uint32_t timeout_ms) {
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModeListener);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->listener.wait_event(timeout_ms);
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_listener_tx(const uint8_t* tx_data, size_t tx_bits) {
|
|
furi_check(tx_data);
|
|
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModeListener);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->listener.tx(handle, tx_data, tx_bits);
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_common_fifo_rx(
|
|
FuriHalSpiBusHandle* handle,
|
|
uint8_t* rx_data,
|
|
size_t rx_data_size,
|
|
size_t* rx_bits) {
|
|
FuriHalNfcError error = FuriHalNfcErrorNone;
|
|
|
|
if(!st25r3916_read_fifo(handle, rx_data, rx_data_size, rx_bits)) {
|
|
error = FuriHalNfcErrorBufferOverflow;
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_listener_rx(uint8_t* rx_data, size_t rx_data_size, size_t* rx_bits) {
|
|
furi_check(rx_data);
|
|
furi_check(rx_bits);
|
|
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModeListener);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->listener.rx(
|
|
handle, rx_data, rx_data_size, rx_bits);
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_trx_reset(void) {
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
st25r3916_direct_cmd(handle, ST25R3916_CMD_STOP);
|
|
|
|
return FuriHalNfcErrorNone;
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_listener_sleep(void) {
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModeListener);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->listener.sleep(handle);
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_listener_idle(void) {
|
|
furi_check(furi_hal_nfc.mode == FuriHalNfcModeListener);
|
|
furi_check(furi_hal_nfc.tech < FuriHalNfcTechNum);
|
|
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
return furi_hal_nfc_tech[furi_hal_nfc.tech]->listener.idle(handle);
|
|
}
|
|
|
|
FuriHalNfcError furi_hal_nfc_listener_enable_rx(void) {
|
|
FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
|
|
|
|
st25r3916_direct_cmd(handle, ST25R3916_CMD_UNMASK_RECEIVE_DATA);
|
|
|
|
return FuriHalNfcErrorNone;
|
|
}
|