mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-12-26 20:53:07 +00:00
3de856f8d5
* FuriHal: add bus abstraction and port some subsystem to it * Make PVS happy, cleanup code * Update API symbols for f18 * F18: backport bus changes from f7 * Revert to STOP2 sleep mode * Fix downgrading the firmware via updater * Port iButton TIM1 to furi_hal_bus * Port Infrared TIM1 and TIM2 to furi_hal_bus * Just enable the timer bus * Port furi_hal_pwm to bus API * Fix include statement * Port furi_hal_rfid to bus API * Port furi_hal_subghz and others to bus API * Remove unneeded include * Improve furi_hal_infrared defines * Reset LPTIM1 via furi_hal_bus API * Crash when trying to enable an already enabled peripheral * Better defines * Improved checks * Lots of macro wrappers * Copy spi changes for f18 * Fix crashes in LFRFID system * Fix crashes in NFC system * Improve comments * Create FuriHalBus.md * Update FuriHalBus.md * Fix crash when launching updater * Documentation: couple small fixes in FuriHalBus * FuriHal: fix copypaste in furi_hal_rfid_tim_reset * FuriHal: reset radio core related peripherals on restart * FuriHalBus: is enabled routine and bug fix for uart * RFID HAL: accomodate furi hal bus Co-authored-by: Georgii Surkov <georgii.surkov@outlook.com> Co-authored-by: Georgii Surkov <37121527+gsurkov@users.noreply.github.com> Co-authored-by: SG <who.just.the.doctor@gmail.com>
557 lines
19 KiB
C
557 lines
19 KiB
C
#include <furi_hal_flash.h>
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#include <furi_hal_bt.h>
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#include <furi_hal_power.h>
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#include <furi_hal_cortex.h>
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#include <furi.h>
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#include <ble/ble.h>
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#include <interface/patterns/ble_thread/shci/shci.h>
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#include <stm32wbxx.h>
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#define TAG "FuriHalFlash"
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#define FURI_HAL_CRITICAL_MSG "Critical flash operation fail"
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#define FURI_HAL_FLASH_READ_BLOCK (8U)
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#define FURI_HAL_FLASH_WRITE_BLOCK (8U)
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#define FURI_HAL_FLASH_PAGE_SIZE (4096U)
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#define FURI_HAL_FLASH_CYCLES_COUNT (10000U)
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#define FURI_HAL_FLASH_TIMEOUT (1000U)
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#define FURI_HAL_FLASH_KEY1 (0x45670123U)
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#define FURI_HAL_FLASH_KEY2 (0xCDEF89ABU)
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#define FURI_HAL_FLASH_TOTAL_PAGES (256U)
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#define FURI_HAL_FLASH_SR_ERRORS \
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(FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | FLASH_SR_SIZERR | \
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FLASH_SR_PGSERR | FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | FLASH_SR_OPTVERR)
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#define FURI_HAL_FLASH_OPT_KEY1 (0x08192A3BU)
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#define FURI_HAL_FLASH_OPT_KEY2 (0x4C5D6E7FU)
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#define FURI_HAL_FLASH_OB_TOTAL_WORDS (0x80 / (sizeof(uint32_t) * 2))
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/* STM32CubeWB/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_RfWithFlash/Core/Src/flash_driver.c
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* ProcessSingleFlashOperation, quote:
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> In most BLE application, the flash should not be blocked by the CPU2 longer than FLASH_TIMEOUT_VALUE (1000ms)
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> However, it could be that for some marginal application, this time is longer.
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> ... there is no other way than waiting the operation to be completed.
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> If for any reason this test is never passed, this means there is a failure in the system and there is no other
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> way to recover than applying a device reset.
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*/
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#define FURI_HAL_FLASH_C2_LOCK_TIMEOUT_MS (3000U) /* 3 seconds */
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#define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__)&0x7U) == (0x00UL))
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#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) \
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(((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && \
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(((__VALUE__) % 8UL) == 0UL))
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/* Free flash space borders, exported by linker */
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extern const void __free_flash_start__;
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size_t furi_hal_flash_get_base() {
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return FLASH_BASE;
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}
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size_t furi_hal_flash_get_read_block_size() {
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return FURI_HAL_FLASH_READ_BLOCK;
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}
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size_t furi_hal_flash_get_write_block_size() {
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return FURI_HAL_FLASH_WRITE_BLOCK;
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}
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size_t furi_hal_flash_get_page_size() {
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return FURI_HAL_FLASH_PAGE_SIZE;
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}
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size_t furi_hal_flash_get_cycles_count() {
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return FURI_HAL_FLASH_CYCLES_COUNT;
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}
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const void* furi_hal_flash_get_free_start_address() {
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return &__free_flash_start__;
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}
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const void* furi_hal_flash_get_free_end_address() {
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uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
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uint32_t sfsa = (READ_BIT(sfr_reg_val, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
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return (const void*)((sfsa * FURI_HAL_FLASH_PAGE_SIZE) + FLASH_BASE);
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}
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size_t furi_hal_flash_get_free_page_start_address() {
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size_t start = (size_t)furi_hal_flash_get_free_start_address();
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size_t page_start = start - start % FURI_HAL_FLASH_PAGE_SIZE;
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if(page_start != start) {
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page_start += FURI_HAL_FLASH_PAGE_SIZE;
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}
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return page_start;
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}
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size_t furi_hal_flash_get_free_page_count() {
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size_t end = (size_t)furi_hal_flash_get_free_end_address();
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size_t page_start = (size_t)furi_hal_flash_get_free_page_start_address();
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return (end - page_start) / FURI_HAL_FLASH_PAGE_SIZE;
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}
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void furi_hal_flash_init() {
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/* Errata 2.2.9, Flash OPTVERR flag is always set after system reset */
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// WRITE_REG(FLASH->SR, FLASH_SR_OPTVERR);
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/* Actually, reset all error flags on start */
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if(READ_BIT(FLASH->SR, FURI_HAL_FLASH_SR_ERRORS)) {
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FURI_LOG_E(TAG, "FLASH->SR 0x%08lX", FLASH->SR);
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WRITE_REG(FLASH->SR, FURI_HAL_FLASH_SR_ERRORS);
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}
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}
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static void furi_hal_flash_unlock() {
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/* verify Flash is locked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U);
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/* Authorize the FLASH Registers access */
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WRITE_REG(FLASH->KEYR, FURI_HAL_FLASH_KEY1);
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__ISB();
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WRITE_REG(FLASH->KEYR, FURI_HAL_FLASH_KEY2);
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/* verify Flash is unlocked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U);
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}
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static void furi_hal_flash_lock(void) {
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/* verify Flash is unlocked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U);
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/* Set the LOCK Bit to lock the FLASH Registers access */
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/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
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SET_BIT(FLASH->CR, FLASH_CR_LOCK);
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/* verify Flash is locked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U);
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}
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static void furi_hal_flash_begin_with_core2(bool erase_flag) {
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furi_hal_power_insomnia_enter();
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/* Take flash controller ownership */
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while(LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) != 0) {
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furi_thread_yield();
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}
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/* Unlock flash operation */
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furi_hal_flash_unlock();
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/* Erase activity notification */
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if(erase_flag) SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON);
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/* 64mHz 5us core2 flag protection */
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for(volatile uint32_t i = 0; i < 35; i++)
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;
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FuriHalCortexTimer timer = furi_hal_cortex_timer_get(FURI_HAL_FLASH_C2_LOCK_TIMEOUT_MS * 1000);
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while(true) {
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/* Wait till flash controller become usable */
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while(LL_FLASH_IsActiveFlag_OperationSuspended()) {
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furi_check(!furi_hal_cortex_timer_is_expired(timer));
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furi_thread_yield();
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};
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/* Just a little more love */
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taskENTER_CRITICAL();
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/* Actually we already have mutex for it, but specification is specification */
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if(LL_HSEM_IsSemaphoreLocked(HSEM, CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID)) {
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taskEXIT_CRITICAL();
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furi_check(!furi_hal_cortex_timer_is_expired(timer));
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furi_thread_yield();
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continue;
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}
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/* Take sempahopre and prevent core2 from anything funky */
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if(LL_HSEM_1StepLock(HSEM, CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) != 0) {
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taskEXIT_CRITICAL();
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furi_check(!furi_hal_cortex_timer_is_expired(timer));
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furi_thread_yield();
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continue;
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}
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break;
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}
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}
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static void furi_hal_flash_begin(bool erase_flag) {
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/* Acquire dangerous ops mutex */
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furi_hal_bt_lock_core2();
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/* If Core2 is running use IPC locking */
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if(furi_hal_bt_is_alive()) {
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furi_hal_flash_begin_with_core2(erase_flag);
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} else {
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furi_hal_flash_unlock();
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}
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}
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static void furi_hal_flash_end_with_core2(bool erase_flag) {
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/* Funky ops are ok at this point */
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, 0);
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/* Task switching is ok */
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taskEXIT_CRITICAL();
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/* Doesn't make much sense, does it? */
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while(READ_BIT(FLASH->SR, FLASH_SR_BSY)) {
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furi_thread_yield();
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}
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/* Erase activity over, core2 can continue */
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if(erase_flag) SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF);
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/* Lock flash controller */
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furi_hal_flash_lock();
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/* Release flash controller ownership */
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
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furi_hal_power_insomnia_exit();
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}
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static void furi_hal_flash_end(bool erase_flag) {
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/* If Core2 is running - use IPC locking */
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if(furi_hal_bt_is_alive()) {
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furi_hal_flash_end_with_core2(erase_flag);
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} else {
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furi_hal_flash_lock();
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}
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/* Release dangerous ops mutex */
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furi_hal_bt_unlock_core2();
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}
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static void furi_hal_flush_cache(void) {
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/* Flush instruction cache */
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if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) == FLASH_ACR_ICEN) {
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/* Disable instruction cache */
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LL_FLASH_DisableInstCache();
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/* Reset instruction cache */
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LL_FLASH_EnableInstCacheReset();
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LL_FLASH_DisableInstCacheReset();
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/* Enable instruction cache */
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LL_FLASH_EnableInstCache();
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}
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/* Flush data cache */
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if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) == FLASH_ACR_DCEN) {
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/* Disable data cache */
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LL_FLASH_DisableDataCache();
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/* Reset data cache */
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LL_FLASH_EnableDataCacheReset();
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LL_FLASH_DisableDataCacheReset();
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/* Enable data cache */
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LL_FLASH_EnableDataCache();
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}
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}
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bool furi_hal_flash_wait_last_operation(uint32_t timeout) {
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uint32_t error = 0;
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/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
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Even if the FLASH operation fails, the BUSY flag will be reset and an error
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flag will be set */
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FuriHalCortexTimer timer = furi_hal_cortex_timer_get(timeout * 1000);
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while(READ_BIT(FLASH->SR, FLASH_SR_BSY)) {
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if(furi_hal_cortex_timer_is_expired(timer)) {
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return false;
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}
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}
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/* Check FLASH operation error flags */
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error = FLASH->SR;
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/* Check FLASH End of Operation flag */
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if((error & FLASH_SR_EOP) != 0U) {
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/* Clear FLASH End of Operation pending bit */
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CLEAR_BIT(FLASH->SR, FLASH_SR_EOP);
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}
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/* Now update error variable to only error value */
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error &= FURI_HAL_FLASH_SR_ERRORS;
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furi_check(error == 0);
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/* clear error flags */
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CLEAR_BIT(FLASH->SR, error);
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/* Wait for control register to be written */
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timer = furi_hal_cortex_timer_get(timeout * 1000);
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while(READ_BIT(FLASH->SR, FLASH_SR_CFGBSY)) {
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if(furi_hal_cortex_timer_is_expired(timer)) {
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return false;
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}
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}
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return true;
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}
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void furi_hal_flash_erase(uint8_t page) {
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furi_hal_flash_begin(true);
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/* Ensure that controller state is valid */
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furi_check(FLASH->SR == 0);
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/* Verify that next operation can be proceed */
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furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
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/* Select page and start operation */
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MODIFY_REG(
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FLASH->CR, FLASH_CR_PNB, ((page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT));
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/* Wait for last operation to be completed */
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furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
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/* If operation is completed or interrupted, disable the Page Erase Bit */
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CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
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/* Flush the caches to be sure of the data consistency */
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furi_hal_flush_cache();
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furi_hal_flash_end(true);
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}
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static inline void furi_hal_flash_write_dword_internal_nowait(size_t address, uint64_t* data) {
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/* Program first word */
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*(uint32_t*)address = (uint32_t)*data;
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/* Barrier to ensure programming is performed in 2 steps, in right order
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(independently of compiler optimization behavior) */
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__ISB();
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/* Program second word */
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*(uint32_t*)(address + 4U) = (uint32_t)(*data >> 32U);
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}
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static inline void furi_hal_flash_write_dword_internal(size_t address, uint64_t* data) {
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furi_hal_flash_write_dword_internal_nowait(address, data);
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/* Wait for last operation to be completed */
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furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
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}
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void furi_hal_flash_write_dword(size_t address, uint64_t data) {
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furi_hal_flash_begin(false);
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/* Ensure that controller state is valid */
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furi_check(FLASH->SR == 0);
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/* Check the parameters */
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furi_check(IS_ADDR_ALIGNED_64BITS(address));
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furi_check(IS_FLASH_PROGRAM_ADDRESS(address));
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/* Set PG bit */
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SET_BIT(FLASH->CR, FLASH_CR_PG);
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/* Do the thing */
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furi_hal_flash_write_dword_internal(address, &data);
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/* If the program operation is completed, disable the PG or FSTPG Bit */
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CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
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furi_hal_flash_end(false);
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/* Wait for last operation to be completed */
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furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
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}
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static size_t furi_hal_flash_get_page_address(uint8_t page) {
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return furi_hal_flash_get_base() + page * FURI_HAL_FLASH_PAGE_SIZE;
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}
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void furi_hal_flash_program_page(const uint8_t page, const uint8_t* data, uint16_t _length) {
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uint16_t length = _length;
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furi_check(length <= FURI_HAL_FLASH_PAGE_SIZE);
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furi_hal_flash_erase(page);
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furi_hal_flash_begin(false);
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furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
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/* Ensure that controller state is valid */
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furi_check(FLASH->SR == 0);
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size_t page_start_address = furi_hal_flash_get_page_address(page);
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size_t length_written = 0;
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const uint16_t FAST_PROG_BLOCK_SIZE = 512;
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const uint8_t DWORD_PROG_BLOCK_SIZE = 8;
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/* Write as much data as we can in fast mode */
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if(length >= FAST_PROG_BLOCK_SIZE) {
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taskENTER_CRITICAL();
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/* Enable fast flash programming mode */
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SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
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while(length_written < (length / FAST_PROG_BLOCK_SIZE * FAST_PROG_BLOCK_SIZE)) {
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/* No context switch in the middle of the operation */
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furi_hal_flash_write_dword_internal_nowait(
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page_start_address + length_written, (uint64_t*)(data + length_written));
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length_written += DWORD_PROG_BLOCK_SIZE;
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if((length_written % FAST_PROG_BLOCK_SIZE) == 0) {
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/* Wait for block operation to be completed */
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furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
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}
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}
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CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
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taskEXIT_CRITICAL();
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}
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/* Enable regular (dword) programming mode */
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SET_BIT(FLASH->CR, FLASH_CR_PG);
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if((length % FAST_PROG_BLOCK_SIZE) != 0) {
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/* Write tail in regular, dword mode */
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while(length_written < (length / DWORD_PROG_BLOCK_SIZE * DWORD_PROG_BLOCK_SIZE)) {
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furi_hal_flash_write_dword_internal(
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page_start_address + length_written, (uint64_t*)&data[length_written]);
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length_written += DWORD_PROG_BLOCK_SIZE;
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}
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}
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if((length % DWORD_PROG_BLOCK_SIZE) != 0) {
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/* there are more bytes, not fitting into dwords */
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uint64_t tail_data = 0;
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for(int32_t tail_i = 0; tail_i < (length % DWORD_PROG_BLOCK_SIZE); ++tail_i) {
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tail_data |= (((uint64_t)data[length_written + tail_i]) << (tail_i * 8));
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}
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furi_hal_flash_write_dword_internal(page_start_address + length_written, &tail_data);
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}
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/* Disable the PG Bit */
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CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
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furi_hal_flash_end(false);
|
|
}
|
|
|
|
int16_t furi_hal_flash_get_page_number(size_t address) {
|
|
const size_t flash_base = furi_hal_flash_get_base();
|
|
if((address < flash_base) ||
|
|
(address > flash_base + FURI_HAL_FLASH_TOTAL_PAGES * FURI_HAL_FLASH_PAGE_SIZE)) {
|
|
return -1;
|
|
}
|
|
|
|
return (address - flash_base) / FURI_HAL_FLASH_PAGE_SIZE;
|
|
}
|
|
|
|
uint32_t furi_hal_flash_ob_get_word(size_t word_idx, bool complementary) {
|
|
furi_check(word_idx <= FURI_HAL_FLASH_OB_TOTAL_WORDS);
|
|
const uint32_t* ob_data = (const uint32_t*)(OPTION_BYTE_BASE);
|
|
size_t raw_word_idx = word_idx * 2;
|
|
if(complementary) {
|
|
raw_word_idx += 1;
|
|
}
|
|
return ob_data[raw_word_idx];
|
|
}
|
|
|
|
void furi_hal_flash_ob_unlock() {
|
|
furi_check(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U);
|
|
furi_hal_flash_begin(true);
|
|
WRITE_REG(FLASH->OPTKEYR, FURI_HAL_FLASH_OPT_KEY1);
|
|
__ISB();
|
|
WRITE_REG(FLASH->OPTKEYR, FURI_HAL_FLASH_OPT_KEY2);
|
|
/* verify OB area is unlocked */
|
|
furi_check(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U);
|
|
}
|
|
|
|
void furi_hal_flash_ob_lock() {
|
|
furi_check(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U);
|
|
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
|
|
furi_hal_flash_end(true);
|
|
furi_check(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U);
|
|
}
|
|
|
|
typedef enum {
|
|
FuriHalFlashObInvalid,
|
|
FuriHalFlashObRegisterUserRead,
|
|
FuriHalFlashObRegisterPCROP1AStart,
|
|
FuriHalFlashObRegisterPCROP1AEnd,
|
|
FuriHalFlashObRegisterWRPA,
|
|
FuriHalFlashObRegisterWRPB,
|
|
FuriHalFlashObRegisterPCROP1BStart,
|
|
FuriHalFlashObRegisterPCROP1BEnd,
|
|
FuriHalFlashObRegisterIPCCMail,
|
|
FuriHalFlashObRegisterSecureFlash,
|
|
FuriHalFlashObRegisterC2Opts,
|
|
} FuriHalFlashObRegister;
|
|
|
|
typedef struct {
|
|
FuriHalFlashObRegister ob_reg;
|
|
uint32_t* ob_register_address;
|
|
} FuriHalFlashObMapping;
|
|
|
|
#define OB_REG_DEF(INDEX, REG) \
|
|
{ .ob_reg = INDEX, .ob_register_address = (uint32_t*)(REG) }
|
|
|
|
static const FuriHalFlashObMapping furi_hal_flash_ob_reg_map[FURI_HAL_FLASH_OB_TOTAL_WORDS] = {
|
|
OB_REG_DEF(FuriHalFlashObRegisterUserRead, (&FLASH->OPTR)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterPCROP1AStart, (&FLASH->PCROP1ASR)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterPCROP1AEnd, (&FLASH->PCROP1AER)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterWRPA, (&FLASH->WRP1AR)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterWRPB, (&FLASH->WRP1BR)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterPCROP1BStart, (&FLASH->PCROP1BSR)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterPCROP1BEnd, (&FLASH->PCROP1BER)),
|
|
|
|
OB_REG_DEF(FuriHalFlashObInvalid, (NULL)),
|
|
OB_REG_DEF(FuriHalFlashObInvalid, (NULL)),
|
|
OB_REG_DEF(FuriHalFlashObInvalid, (NULL)),
|
|
OB_REG_DEF(FuriHalFlashObInvalid, (NULL)),
|
|
OB_REG_DEF(FuriHalFlashObInvalid, (NULL)),
|
|
OB_REG_DEF(FuriHalFlashObInvalid, (NULL)),
|
|
|
|
OB_REG_DEF(FuriHalFlashObRegisterIPCCMail, (&FLASH->IPCCBR)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterSecureFlash, (NULL)),
|
|
OB_REG_DEF(FuriHalFlashObRegisterC2Opts, (NULL)),
|
|
};
|
|
#undef OB_REG_DEF
|
|
|
|
void furi_hal_flash_ob_apply() {
|
|
furi_hal_flash_ob_unlock();
|
|
/* OBL_LAUNCH: When set to 1, this bit forces the option byte reloading.
|
|
* It cannot be written if OPTLOCK is set */
|
|
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
|
furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
|
|
furi_hal_flash_ob_lock();
|
|
}
|
|
|
|
bool furi_hal_flash_ob_set_word(size_t word_idx, const uint32_t value) {
|
|
furi_check(word_idx < FURI_HAL_FLASH_OB_TOTAL_WORDS);
|
|
|
|
const FuriHalFlashObMapping* reg_def = &furi_hal_flash_ob_reg_map[word_idx];
|
|
if(reg_def->ob_register_address == NULL) {
|
|
FURI_LOG_E(TAG, "Attempt to set RO OB word %d", word_idx);
|
|
return false;
|
|
}
|
|
|
|
FURI_LOG_W(
|
|
TAG,
|
|
"Setting OB reg %d for word %d (addr 0x%08lX) to 0x%08lX",
|
|
reg_def->ob_reg,
|
|
word_idx,
|
|
(uint32_t)reg_def->ob_register_address,
|
|
value);
|
|
|
|
/* 1. Clear OPTLOCK option lock bit with the clearing sequence */
|
|
furi_hal_flash_ob_unlock();
|
|
|
|
/* 2. Write the desired options value in the options registers */
|
|
*reg_def->ob_register_address = value;
|
|
|
|
/* 3. Check that no Flash memory operation is on going by checking the BSY && PESD */
|
|
furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
|
|
while(LL_FLASH_IsActiveFlag_OperationSuspended()) {
|
|
furi_thread_yield();
|
|
};
|
|
|
|
/* 4. Set the Options start bit OPTSTRT */
|
|
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
|
/* 5. Wait for the BSY bit to be cleared. */
|
|
furi_check(furi_hal_flash_wait_last_operation(FURI_HAL_FLASH_TIMEOUT));
|
|
furi_hal_flash_ob_lock();
|
|
return true;
|
|
}
|
|
|
|
const FuriHalFlashRawOptionByteData* furi_hal_flash_ob_get_raw_ptr() {
|
|
return (const FuriHalFlashRawOptionByteData*)OPTION_BYTE_BASE;
|
|
}
|