mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-12-21 02:03:18 +00:00
514 lines
No EOL
16 KiB
C
514 lines
No EOL
16 KiB
C
#include "nrf24.h"
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#include <furi.h>
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#include <furi_hal.h>
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#include <furi_hal_resources.h>
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#include <assert.h>
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#include <string.h>
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void nrf24_init() {
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furi_hal_spi_bus_handle_init(nrf24_HANDLE);
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furi_hal_spi_acquire(nrf24_HANDLE);
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furi_hal_gpio_init(nrf24_CE_PIN, GpioModeOutputPushPull, GpioPullUp, GpioSpeedVeryHigh);
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furi_hal_gpio_write(nrf24_CE_PIN, false);
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}
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void nrf24_spi_trx(
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FuriHalSpiBusHandle* handle,
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uint8_t* tx,
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uint8_t* rx,
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uint8_t size,
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uint32_t timeout) {
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UNUSED(timeout);
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furi_hal_gpio_write(handle->cs, false);
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furi_hal_spi_bus_trx(handle, tx, rx, size, nrf24_TIMEOUT);
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furi_hal_gpio_write(handle->cs, true);
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}
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uint8_t nrf24_write_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t data) {
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uint8_t tx[2] = {W_REGISTER | (REGISTER_MASK & reg), data};
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uint8_t rx[2] = {0};
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nrf24_spi_trx(handle, tx, rx, 2, nrf24_TIMEOUT);
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return rx[0];
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}
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uint8_t
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nrf24_write_buf_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
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uint8_t tx[size + 1];
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uint8_t rx[size + 1];
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memset(rx, 0, size + 1);
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tx[0] = W_REGISTER | (REGISTER_MASK & reg);
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memcpy(&tx[1], data, size);
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nrf24_spi_trx(handle, tx, rx, size + 1, nrf24_TIMEOUT);
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return rx[0];
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}
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uint8_t nrf24_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
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uint8_t tx[size + 1];
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uint8_t rx[size + 1];
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memset(rx, 0, size + 1);
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tx[0] = R_REGISTER | (REGISTER_MASK & reg);
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memset(&tx[1], 0, size);
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nrf24_spi_trx(handle, tx, rx, size + 1, nrf24_TIMEOUT);
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memcpy(data, &rx[1], size);
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return rx[0];
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}
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uint8_t nrf24_flush_rx(FuriHalSpiBusHandle* handle) {
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uint8_t tx[] = {FLUSH_RX};
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uint8_t rx[] = {0};
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nrf24_spi_trx(handle, tx, rx, 1, nrf24_TIMEOUT);
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return rx[0];
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}
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uint8_t nrf24_flush_tx(FuriHalSpiBusHandle* handle) {
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uint8_t tx[] = {FLUSH_TX};
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uint8_t rx[] = {0};
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nrf24_spi_trx(handle, tx, rx, 1, nrf24_TIMEOUT);
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return rx[0];
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}
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uint8_t nrf24_get_maclen(FuriHalSpiBusHandle* handle) {
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uint8_t maclen;
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nrf24_read_reg(handle, REG_SETUP_AW, &maclen, 1);
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maclen &= 3;
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return maclen + 2;
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}
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uint8_t nrf24_set_maclen(FuriHalSpiBusHandle* handle, uint8_t maclen) {
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assert(maclen > 1 && maclen < 6);
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uint8_t status = 0;
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status = nrf24_write_reg(handle, REG_SETUP_AW, maclen - 2);
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return status;
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}
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uint8_t nrf24_status(FuriHalSpiBusHandle* handle) {
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uint8_t status;
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uint8_t tx[] = {R_REGISTER | (REGISTER_MASK & REG_STATUS)};
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nrf24_spi_trx(handle, tx, &status, 1, nrf24_TIMEOUT);
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return status;
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}
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uint32_t nrf24_get_rate(FuriHalSpiBusHandle* handle) {
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uint8_t setup = 0;
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uint32_t rate = 0;
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nrf24_read_reg(handle, REG_RF_SETUP, &setup, 1);
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setup &= 0x28;
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if(setup == 0x20)
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rate = 250000; // 250kbps
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else if(setup == 0x08)
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rate = 2000000; // 2Mbps
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else if(setup == 0x00)
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rate = 1000000; // 1Mbps
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return rate;
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}
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uint8_t nrf24_set_rate(FuriHalSpiBusHandle* handle, uint32_t rate) {
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uint8_t r6 = 0;
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uint8_t status = 0;
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if(!rate) rate = 2000000;
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nrf24_read_reg(handle, REG_RF_SETUP, &r6, 1); // RF_SETUP register
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r6 = r6 & (~0x28); // Clear rate fields.
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if(rate == 2000000)
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r6 = r6 | 0x08;
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else if(rate == 1000000)
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r6 = r6;
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else if(rate == 250000)
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r6 = r6 | 0x20;
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status = nrf24_write_reg(handle, REG_RF_SETUP, r6); // Write new rate.
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return status;
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}
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uint8_t nrf24_get_chan(FuriHalSpiBusHandle* handle) {
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uint8_t channel = 0;
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nrf24_read_reg(handle, REG_RF_CH, &channel, 1);
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return channel;
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}
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uint8_t nrf24_set_chan(FuriHalSpiBusHandle* handle, uint8_t chan) {
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uint8_t status;
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status = nrf24_write_reg(handle, REG_RF_CH, chan);
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return status;
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}
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uint8_t nrf24_get_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
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uint8_t size = 0;
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uint8_t status = 0;
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size = nrf24_get_maclen(handle);
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status = nrf24_read_reg(handle, REG_RX_ADDR_P0, mac, size);
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return status;
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}
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uint8_t nrf24_set_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
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uint8_t status = 0;
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uint8_t clearmac[] = {0, 0, 0, 0, 0};
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nrf24_set_maclen(handle, size);
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nrf24_write_buf_reg(handle, REG_RX_ADDR_P0, clearmac, 5);
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status = nrf24_write_buf_reg(handle, REG_RX_ADDR_P0, mac, size);
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return status;
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}
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uint8_t nrf24_get_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
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uint8_t size = 0;
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uint8_t status = 0;
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size = nrf24_get_maclen(handle);
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status = nrf24_read_reg(handle, REG_TX_ADDR, mac, size);
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return status;
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}
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uint8_t nrf24_set_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
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uint8_t status = 0;
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uint8_t clearmac[] = {0, 0, 0, 0, 0};
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nrf24_set_maclen(handle, size);
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nrf24_write_buf_reg(handle, REG_TX_ADDR, clearmac, 5);
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status = nrf24_write_buf_reg(handle, REG_TX_ADDR, mac, size);
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return status;
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}
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uint8_t nrf24_get_packetlen(FuriHalSpiBusHandle* handle) {
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uint8_t len = 0;
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nrf24_read_reg(handle, RX_PW_P0, &len, 1);
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return len;
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}
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uint8_t nrf24_set_packetlen(FuriHalSpiBusHandle* handle, uint8_t len) {
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uint8_t status = 0;
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status = nrf24_write_reg(handle, RX_PW_P0, len);
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return status;
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}
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uint8_t
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nrf24_rxpacket(FuriHalSpiBusHandle* handle, uint8_t* packet, uint8_t* packetsize, bool full) {
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uint8_t status = 0;
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uint8_t size = 0;
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uint8_t tx_pl_wid[] = {R_RX_PL_WID, 0};
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uint8_t rx_pl_wid[] = {0, 0};
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uint8_t tx_cmd[33] = {0}; // 32 max payload size + 1 for command
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uint8_t tmp_packet[33] = {0};
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status = nrf24_status(handle);
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if(status & 0x40) {
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if(full)
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size = nrf24_get_packetlen(handle);
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else {
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nrf24_spi_trx(handle, tx_pl_wid, rx_pl_wid, 2, nrf24_TIMEOUT);
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size = rx_pl_wid[1];
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}
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tx_cmd[0] = R_RX_PAYLOAD;
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nrf24_spi_trx(handle, tx_cmd, tmp_packet, size + 1, nrf24_TIMEOUT);
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nrf24_write_reg(handle, REG_STATUS, 0x40); // clear bit.
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memcpy(packet, &tmp_packet[1], size);
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} else if(status == 0) {
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nrf24_flush_rx(handle);
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nrf24_write_reg(handle, REG_STATUS, 0x40); // clear bit.
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}
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*packetsize = size;
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return status;
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}
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uint8_t nrf24_txpacket(FuriHalSpiBusHandle* handle, uint8_t* payload, uint8_t size, bool ack) {
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uint8_t status = 0;
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uint8_t tx[size + 1];
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uint8_t rx[size + 1];
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memset(tx, 0, size + 1);
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memset(rx, 0, size + 1);
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if(!ack)
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tx[0] = W_TX_PAYLOAD_NOACK;
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else
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tx[0] = W_TX_PAYLOAD;
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memcpy(&tx[1], payload, size);
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nrf24_spi_trx(handle, tx, rx, size + 1, nrf24_TIMEOUT);
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nrf24_set_tx_mode(handle);
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while(!(status & (TX_DS | MAX_RT))) status = nrf24_status(handle);
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if(status & MAX_RT) nrf24_flush_tx(handle);
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nrf24_set_idle(handle);
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nrf24_write_reg(handle, REG_STATUS, TX_DS | MAX_RT);
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return status & TX_DS;
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}
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uint8_t nrf24_power_up(FuriHalSpiBusHandle* handle) {
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uint8_t status = 0;
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uint8_t cfg = 0;
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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cfg = cfg | 2;
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status = nrf24_write_reg(handle, REG_CONFIG, cfg);
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furi_delay_ms(5000);
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return status;
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}
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uint8_t nrf24_set_idle(FuriHalSpiBusHandle* handle) {
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uint8_t status = 0;
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uint8_t cfg = 0;
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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cfg &= 0xfc; // clear bottom two bits to power down the radio
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status = nrf24_write_reg(handle, REG_CONFIG, cfg);
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//nr204_write_reg(handle, REG_EN_RXADDR, 0x0);
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furi_hal_gpio_write(nrf24_CE_PIN, false);
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return status;
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}
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uint8_t nrf24_set_rx_mode(FuriHalSpiBusHandle* handle) {
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uint8_t status = 0;
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uint8_t cfg = 0;
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//status = nrf24_write_reg(handle, REG_CONFIG, 0x0F); // enable 2-byte CRC, PWR_UP, and PRIM_RX
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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cfg |= 0x03; // PWR_UP, and PRIM_RX
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status = nrf24_write_reg(handle, REG_CONFIG, cfg);
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//nr204_write_reg(REG_EN_RXADDR, 0x03) // Set RX Pipe 0 and 1
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furi_hal_gpio_write(nrf24_CE_PIN, true);
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furi_delay_ms(2000);
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return status;
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}
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uint8_t nrf24_set_tx_mode(FuriHalSpiBusHandle* handle) {
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uint8_t status = 0;
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uint8_t cfg = 0;
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furi_hal_gpio_write(nrf24_CE_PIN, false);
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nrf24_write_reg(handle, REG_STATUS, 0x30);
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//status = nrf24_write_reg(handle, REG_CONFIG, 0x0E); // enable 2-byte CRC, PWR_UP
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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cfg &= 0xfe; // disable PRIM_RX
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cfg |= 0x02; // PWR_UP
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status = nrf24_write_reg(handle, REG_CONFIG, cfg);
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furi_hal_gpio_write(nrf24_CE_PIN, true);
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furi_delay_ms(2);
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return status;
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}
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void nrf24_configure(
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FuriHalSpiBusHandle* handle,
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uint8_t rate,
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uint8_t* srcmac,
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uint8_t* dstmac,
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uint8_t maclen,
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uint8_t channel,
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bool noack,
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bool disable_aa) {
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assert(channel <= 125);
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assert(rate == 1 || rate == 2);
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if(rate == 2)
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rate = 8; // 2Mbps
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else
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rate = 0; // 1Mbps
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nrf24_write_reg(handle, REG_CONFIG, 0x00); // Stop nRF
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nrf24_set_idle(handle);
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nrf24_write_reg(handle, REG_STATUS, 0x1c); // clear interrupts
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if(disable_aa)
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nrf24_write_reg(handle, REG_EN_AA, 0x00); // Disable Shockburst
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else
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nrf24_write_reg(handle, REG_EN_AA, 0x1F); // Enable Shockburst
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nrf24_write_reg(handle, REG_DYNPD, 0x3F); // enable dynamic payload length on all pipes
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if(noack)
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nrf24_write_reg(handle, REG_FEATURE, 0x05); // disable payload-with-ack, enable noack
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else {
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nrf24_write_reg(handle, REG_CONFIG, 0x0C); // 2 byte CRC
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nrf24_write_reg(handle, REG_FEATURE, 0x07); // enable dyn payload and ack
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nrf24_write_reg(
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handle, REG_SETUP_RETR, 0x1f); // 15 retries for AA, 500us auto retransmit delay
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}
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nrf24_set_idle(handle);
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nrf24_flush_rx(handle);
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nrf24_flush_tx(handle);
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if(maclen) nrf24_set_maclen(handle, maclen);
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if(srcmac) nrf24_set_src_mac(handle, srcmac, maclen);
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if(dstmac) nrf24_set_dst_mac(handle, dstmac, maclen);
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nrf24_write_reg(handle, REG_RF_CH, channel);
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nrf24_write_reg(handle, REG_RF_SETUP, rate);
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furi_delay_ms(200);
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}
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void nrf24_init_promisc_mode(FuriHalSpiBusHandle* handle, uint8_t channel, uint8_t rate) {
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//uint8_t preamble[] = {0x55, 0x00}; // little endian
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uint8_t preamble[] = {0xAA, 0x00}; // little endian
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//uint8_t preamble[] = {0x00, 0x55}; // little endian
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//uint8_t preamble[] = {0x00, 0xAA}; // little endian
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nrf24_write_reg(handle, REG_CONFIG, 0x00); // Stop nRF
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nrf24_write_reg(handle, REG_STATUS, 0x1c); // clear interrupts
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nrf24_write_reg(handle, REG_DYNPD, 0x0); // disable shockburst
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nrf24_write_reg(handle, REG_EN_AA, 0x00); // Disable Shockburst
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nrf24_write_reg(handle, REG_FEATURE, 0x05); // disable payload-with-ack, enable noack
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nrf24_set_maclen(handle, 2); // shortest address
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nrf24_set_src_mac(handle, preamble, 2); // set src mac to preamble bits to catch everything
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nrf24_set_packetlen(handle, 32); // set max packet length
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nrf24_set_idle(handle);
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nrf24_flush_rx(handle);
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nrf24_flush_tx(handle);
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nrf24_write_reg(handle, REG_RF_CH, channel);
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nrf24_write_reg(handle, REG_RF_SETUP, rate);
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furi_delay_ms(200);
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// prime for RX, no checksum
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nrf24_write_reg(handle, REG_CONFIG, 0x03); // PWR_UP and PRIM_RX, disable AA and CRC
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furi_hal_gpio_write(nrf24_CE_PIN, true);
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furi_delay_ms(2000);
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}
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void hexlify(uint8_t* in, uint8_t size, char* out) {
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memset(out, 0, size * 2);
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for(int i = 0; i < size; i++)
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snprintf(out + strlen(out), sizeof(out + strlen(out)), "%02X", in[i]);
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}
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uint64_t bytes_to_int64(uint8_t* bytes, uint8_t size, bool bigendian) {
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uint64_t ret = 0;
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for(int i = 0; i < size; i++)
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if(bigendian)
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ret |= bytes[i] << ((size - 1 - i) * 8);
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else
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ret |= bytes[i] << (i * 8);
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return ret;
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}
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void int64_to_bytes(uint64_t val, uint8_t* out, bool bigendian) {
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for(int i = 0; i < 8; i++) {
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if(bigendian)
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out[i] = (val >> ((7 - i) * 8)) & 0xff;
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else
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out[i] = (val >> (i * 8)) & 0xff;
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}
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}
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uint32_t bytes_to_int32(uint8_t* bytes, bool bigendian) {
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uint32_t ret = 0;
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for(int i = 0; i < 4; i++)
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if(bigendian)
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ret |= bytes[i] << ((3 - i) * 8);
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else
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ret |= bytes[i] << (i * 8);
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return ret;
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}
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void int32_to_bytes(uint32_t val, uint8_t* out, bool bigendian) {
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for(int i = 0; i < 4; i++) {
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if(bigendian)
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out[i] = (val >> ((3 - i) * 8)) & 0xff;
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else
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out[i] = (val >> (i * 8)) & 0xff;
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}
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}
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uint64_t bytes_to_int16(uint8_t* bytes, bool bigendian) {
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uint16_t ret = 0;
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for(int i = 0; i < 2; i++)
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if(bigendian)
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ret |= bytes[i] << ((1 - i) * 8);
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else
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ret |= bytes[i] << (i * 8);
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return ret;
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}
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void int16_to_bytes(uint16_t val, uint8_t* out, bool bigendian) {
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for(int i = 0; i < 2; i++) {
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if(bigendian)
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out[i] = (val >> ((1 - i) * 8)) & 0xff;
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else
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out[i] = (val >> (i * 8)) & 0xff;
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}
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}
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// handle iffyness with preamble processing sometimes being a bit (literally) off
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void alt_address_old(uint8_t* packet, uint8_t* altaddr) {
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|
uint8_t macmess_hi_b[4];
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|
uint8_t macmess_lo_b[2];
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|
uint32_t macmess_hi;
|
|
uint16_t macmess_lo;
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|
uint8_t preserved;
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|
|
|
// get first 6 bytes into 32-bit and 16-bit variables
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|
memcpy(macmess_hi_b, packet, 4);
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|
memcpy(macmess_lo_b, packet + 4, 2);
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|
|
|
macmess_hi = bytes_to_int32(macmess_hi_b, true);
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|
|
|
//preserve least 7 bits from hi that will be shifted down to lo
|
|
preserved = macmess_hi & 0x7f;
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|
macmess_hi >>= 7;
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|
|
|
macmess_lo = bytes_to_int16(macmess_lo_b, true);
|
|
macmess_lo >>= 7;
|
|
macmess_lo = (preserved << 9) | macmess_lo;
|
|
int32_to_bytes(macmess_hi, macmess_hi_b, true);
|
|
int16_to_bytes(macmess_lo, macmess_lo_b, true);
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|
memcpy(altaddr, &macmess_hi_b[1], 3);
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|
memcpy(altaddr + 3, macmess_lo_b, 2);
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|
}
|
|
|
|
bool validate_address(uint8_t* addr) {
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|
uint8_t bad[][3] = {{0x55, 0x55}, {0xAA, 0xAA}, {0x00, 0x00}, {0xFF, 0xFF}};
|
|
for(int i = 0; i < 4; i++)
|
|
for(int j = 0; j < 2; j++)
|
|
if(!memcmp(addr + j * 2, bad[i], 2)) return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool nrf24_sniff_address(FuriHalSpiBusHandle* handle, uint8_t maclen, uint8_t* address) {
|
|
bool found = false;
|
|
uint8_t packet[32] = {0};
|
|
uint8_t packetsize;
|
|
//char printit[65];
|
|
uint8_t status = 0;
|
|
status = nrf24_rxpacket(handle, packet, &packetsize, true);
|
|
if(status & 0x40) {
|
|
if(validate_address(packet)) {
|
|
for(int i = 0; i < maclen; i++) address[i] = packet[maclen - 1 - i];
|
|
|
|
/*
|
|
alt_address(packet, packet);
|
|
|
|
for(i = 0; i < maclen; i++)
|
|
address[i + 5] = packet[maclen - 1 - i];
|
|
*/
|
|
|
|
//memcpy(address, packet, maclen);
|
|
//hexlify(packet, packetsize, printit);
|
|
found = true;
|
|
}
|
|
}
|
|
|
|
return found;
|
|
}
|
|
|
|
uint8_t nrf24_find_channel(
|
|
FuriHalSpiBusHandle* handle,
|
|
uint8_t* srcmac,
|
|
uint8_t* dstmac,
|
|
uint8_t maclen,
|
|
uint8_t rate,
|
|
uint8_t min_channel,
|
|
uint8_t max_channel,
|
|
bool autoinit) {
|
|
uint8_t ping_packet[] = {0x0f, 0x0f, 0x0f, 0x0f}; // this can be anything, we just need an ack
|
|
uint8_t ch = max_channel + 1; // means fail
|
|
nrf24_configure(handle, rate, srcmac, dstmac, maclen, 2, false, false);
|
|
for(ch = min_channel; ch <= max_channel + 1; ch++) {
|
|
nrf24_write_reg(handle, REG_RF_CH, ch);
|
|
if(nrf24_txpacket(handle, ping_packet, 4, true)) break;
|
|
}
|
|
|
|
if(autoinit) {
|
|
FURI_LOG_I("nrf24", "initializing radio for channel %d", ch);
|
|
nrf24_configure(handle, rate, srcmac, dstmac, maclen, ch, false, false);
|
|
return ch;
|
|
}
|
|
|
|
return ch;
|
|
} |