mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-11-28 07:20:29 +00:00
8fd411097e
* WidGet: fix name Multiline String Element * SubGhz: rename SubGhzProtocol to SubGhzParser and bring it up * SubGhz: a new way to navigate in receiver views * SubGhz: fix syntax * WedGet: add forwarding input type to wedget button callback, fix using a callback in an application * SubGhz: add assertions and status checks * SubGhz: fix syntax * [FL-1790] SubGhz: fix GateTX * SubGhz: add 434.42 MHz frequency support * SubGhz: rename type protocol, add decoder stage names * SubGhz: fix navigation through received signals when changing scenes * SubGhz: fix 2-fsk config Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
730 lines
26 KiB
C
730 lines
26 KiB
C
#include "furi-hal-subghz.h"
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#include <furi-hal-gpio.h>
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#include <furi-hal-spi.h>
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#include <furi-hal-interrupt.h>
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#include <furi-hal-resources.h>
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#include <furi.h>
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#include <cc1101.h>
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#include <stdio.h>
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static volatile SubGhzState furi_hal_subghz_state = SubGhzStateInit;
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static const uint8_t furi_hal_subghz_preset_ook_270khz_async_regs[][2] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
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{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
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{CC1101_MDMCFG4, 0x67}, // Rx BW filter is 270.833333kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
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{CC1101_FREND1, 0xB6}, //
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/* Frequency Synthesizer Calibration, valid for 433.92 */
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{CC1101_FSCAL3, 0xE9},
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{CC1101_FSCAL2, 0x2A},
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{CC1101_FSCAL1, 0x00},
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{CC1101_FSCAL0, 0x1F},
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/* Magic f4ckery */
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{CC1101_TEST2, 0x81}, // FIFOTHR ADC_RETENTION=1 matched value
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{CC1101_TEST1, 0x35}, // FIFOTHR ADC_RETENTION=1 matched value
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{CC1101_TEST0, 0x09}, // VCO selection calibration stage is disabled
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/* End */
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{0, 0},
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};
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static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
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{CC1101_MDMCFG3, 0x32}, // Data rate is 3.79372 kBaud
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{CC1101_MDMCFG4, 0x17}, // Rx BW filter is 650.000kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
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{CC1101_FREND1, 0xB6}, //
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/* Frequency Synthesizer Calibration, valid for 433.92 */
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{CC1101_FSCAL3, 0xE9},
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{CC1101_FSCAL2, 0x2A},
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{CC1101_FSCAL1, 0x00},
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{CC1101_FSCAL0, 0x1F},
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/* Magic f4ckery */
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{CC1101_TEST2, 0x88},
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{CC1101_TEST1, 0x31},
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{CC1101_TEST0, 0x09}, // VCO selection calibration stage is disabled
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/* End */
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{0, 0},
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};
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static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x02},
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{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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{CC1101_MDMCFG3, 0x8B}, // Data rate is 19.5885 kBaud
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{CC1101_MDMCFG4, 0x69}, // Rx BW filter is 270.833333 kHz
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{CC1101_DEVIATN, 0x47}, //Deviation 47.607422 khz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
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{CC1101_FREND1, 0xB6}, //
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/* Frequency Synthesizer Calibration, valid for 433.92 */
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{CC1101_FSCAL3, 0xE9},
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{CC1101_FSCAL2, 0x2A},
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{CC1101_FSCAL1, 0x00},
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{CC1101_FSCAL0, 0x1F},
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/* Magic f4ckery */
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{CC1101_TEST2, 0x81}, // FIFOTHR ADC_RETENTION=1 matched value
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{CC1101_TEST1, 0x35}, // FIFOTHR ADC_RETENTION=1 matched value
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{CC1101_TEST0, 0x09}, // VCO selection calibration stage is disabled
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/* End */
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{0, 0},
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};
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static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
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0x00,
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00};
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static const uint8_t furi_hal_subghz_preset_2fsk_async_patable[8] = {
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00};
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void furi_hal_subghz_init() {
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furi_assert(furi_hal_subghz_state == SubGhzStateInit);
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furi_hal_subghz_state = SubGhzStateIdle;
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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#ifdef FURI_HAL_SUBGHZ_TX_GPIO
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hal_gpio_init(&FURI_HAL_SUBGHZ_TX_GPIO, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
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#endif
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// Reset
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hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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cc1101_reset(device);
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cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
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// Prepare GD0 for power on self test
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hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullNo, GpioSpeedLow);
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// GD0 low
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cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW);
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while(hal_gpio_read(&gpio_cc1101_g0) != false)
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;
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// GD0 high
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cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
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while(hal_gpio_read(&gpio_cc1101_g0) != true)
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;
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// Reset GD0 to floating state
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cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
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hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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// RF switches
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hal_gpio_init(&gpio_rf_sw_0, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
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cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
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// Go to sleep
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cc1101_shutdown(device);
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furi_hal_spi_device_return(device);
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FURI_LOG_I("FuriHalSubGhz", "Init OK");
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}
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void furi_hal_subghz_sleep() {
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furi_assert(furi_hal_subghz_state == SubGhzStateIdle);
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_switch_to_idle(device);
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cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
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hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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cc1101_shutdown(device);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_dump_state() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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printf(
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"[furi_hal_subghz] cc1101 chip %d, version %d\r\n",
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cc1101_get_partnumber(device),
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cc1101_get_version(device));
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
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if(preset == FuriHalSubGhzPresetOok650Async) {
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_650khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
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} else if(preset == FuriHalSubGhzPresetOok270Async) {
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_270khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
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} else if(preset == FuriHalSubGhzPreset2FSKAsync) {
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
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}else {
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furi_crash(NULL);
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}
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}
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uint8_t furi_hal_subghz_get_status() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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CC1101StatusRaw st;
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st.status = cc1101_get_status(device);
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furi_hal_spi_device_return(device);
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return st.status_raw;
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}
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void furi_hal_subghz_load_registers(const uint8_t data[][2]) {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_reset(device);
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uint32_t i = 0;
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while(data[i][0]) {
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cc1101_write_reg(device, data[i][0], data[i][1]);
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i++;
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}
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_load_patable(const uint8_t data[8]) {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_set_pa_table(device, data);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_write_packet(const uint8_t* data, uint8_t size) {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_flush_tx(device);
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cc1101_write_fifo(device, data, size);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_flush_rx() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_flush_rx(device);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_read_packet(uint8_t* data, uint8_t* size) {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_read_fifo(device, data, size);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_shutdown() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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// Reset and shutdown
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cc1101_shutdown(device);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_reset() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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cc1101_switch_to_idle(device);
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cc1101_reset(device);
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cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_idle() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_switch_to_idle(device);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_rx() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_switch_to_rx(device);
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_tx() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_switch_to_tx(device);
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furi_hal_spi_device_return(device);
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}
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float furi_hal_subghz_get_rssi() {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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int32_t rssi_dec = cc1101_get_rssi(device);
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furi_hal_spi_device_return(device);
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float rssi = rssi_dec;
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if(rssi_dec >= 128) {
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rssi = ((rssi - 256.0f) / 2.0f) - 74.0f;
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} else {
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rssi = (rssi / 2.0f) - 74.0f;
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}
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return rssi;
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}
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bool furi_hal_subghz_is_frequency_valid(uint32_t value) {
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if(!(value >= 299999755 && value <= 348000335) &&
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!(value >= 386999938 && value <= 464000000) &&
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!(value >= 778999847 && value <= 928000000)) {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
uint32_t furi_hal_subghz_set_frequency_and_path(uint32_t value) {
|
|
value = furi_hal_subghz_set_frequency(value);
|
|
if(value >= 299999755 && value <= 348000335) {
|
|
furi_hal_subghz_set_path(FuriHalSubGhzPath315);
|
|
} else if(value >= 386999938 && value <= 464000000) {
|
|
furi_hal_subghz_set_path(FuriHalSubGhzPath433);
|
|
} else if(value >= 778999847 && value <= 928000000) {
|
|
furi_hal_subghz_set_path(FuriHalSubGhzPath868);
|
|
} else {
|
|
furi_crash(NULL);
|
|
}
|
|
return value;
|
|
}
|
|
|
|
uint32_t furi_hal_subghz_set_frequency(uint32_t value) {
|
|
const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
|
|
|
|
uint32_t real_frequency = cc1101_set_frequency(device, value);
|
|
cc1101_calibrate(device);
|
|
|
|
while(true) {
|
|
CC1101Status status = cc1101_get_status(device);
|
|
if(status.STATE == CC1101StateIDLE) break;
|
|
}
|
|
|
|
furi_hal_spi_device_return(device);
|
|
|
|
return real_frequency;
|
|
}
|
|
|
|
void furi_hal_subghz_set_path(FuriHalSubGhzPath path) {
|
|
const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
|
|
if(path == FuriHalSubGhzPath433) {
|
|
hal_gpio_write(&gpio_rf_sw_0, 0);
|
|
cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
|
|
} else if(path == FuriHalSubGhzPath315) {
|
|
hal_gpio_write(&gpio_rf_sw_0, 1);
|
|
cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
|
|
} else if(path == FuriHalSubGhzPath868) {
|
|
hal_gpio_write(&gpio_rf_sw_0, 1);
|
|
cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
|
|
} else if(path == FuriHalSubGhzPathIsolate) {
|
|
hal_gpio_write(&gpio_rf_sw_0, 0);
|
|
cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
|
|
} else {
|
|
furi_crash(NULL);
|
|
}
|
|
furi_hal_spi_device_return(device);
|
|
}
|
|
|
|
volatile uint32_t furi_hal_subghz_capture_delta_duration = 0;
|
|
volatile FuriHalSubGhzCaptureCallback furi_hal_subghz_capture_callback = NULL;
|
|
volatile void* furi_hal_subghz_capture_callback_context = NULL;
|
|
|
|
static void furi_hal_subghz_capture_ISR() {
|
|
// Channel 1
|
|
if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
|
|
LL_TIM_ClearFlag_CC1(TIM2);
|
|
furi_hal_subghz_capture_delta_duration = LL_TIM_IC_GetCaptureCH1(TIM2);
|
|
if(furi_hal_subghz_capture_callback) {
|
|
furi_hal_subghz_capture_callback(
|
|
true,
|
|
furi_hal_subghz_capture_delta_duration,
|
|
(void*)furi_hal_subghz_capture_callback_context);
|
|
}
|
|
}
|
|
// Channel 2
|
|
if(LL_TIM_IsActiveFlag_CC2(TIM2)) {
|
|
LL_TIM_ClearFlag_CC2(TIM2);
|
|
if(furi_hal_subghz_capture_callback) {
|
|
furi_hal_subghz_capture_callback(
|
|
false,
|
|
LL_TIM_IC_GetCaptureCH2(TIM2) - furi_hal_subghz_capture_delta_duration,
|
|
(void*)furi_hal_subghz_capture_callback_context);
|
|
}
|
|
}
|
|
}
|
|
|
|
void furi_hal_subghz_start_async_rx(FuriHalSubGhzCaptureCallback callback, void* context) {
|
|
furi_assert(furi_hal_subghz_state == SubGhzStateIdle);
|
|
furi_hal_subghz_state = SubGhzStateAsyncRx;
|
|
|
|
furi_hal_subghz_capture_callback = callback;
|
|
furi_hal_subghz_capture_callback_context = context;
|
|
|
|
hal_gpio_init_ex(
|
|
&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullNo, GpioSpeedLow, GpioAltFn1TIM2);
|
|
|
|
// Timer: base
|
|
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
|
LL_TIM_InitTypeDef TIM_InitStruct = {0};
|
|
TIM_InitStruct.Prescaler = 64 - 1;
|
|
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
|
|
TIM_InitStruct.Autoreload = 0x7FFFFFFE;
|
|
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
|
|
LL_TIM_Init(TIM2, &TIM_InitStruct);
|
|
|
|
// Timer: advanced
|
|
LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
|
|
LL_TIM_DisableARRPreload(TIM2);
|
|
LL_TIM_SetTriggerInput(TIM2, LL_TIM_TS_TI2FP2);
|
|
LL_TIM_SetSlaveMode(TIM2, LL_TIM_SLAVEMODE_RESET);
|
|
LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
|
|
LL_TIM_EnableMasterSlaveMode(TIM2);
|
|
LL_TIM_DisableDMAReq_TRIG(TIM2);
|
|
LL_TIM_DisableIT_TRIG(TIM2);
|
|
|
|
// Timer: channel 1 indirect
|
|
LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ACTIVEINPUT_INDIRECTTI);
|
|
LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ICPSC_DIV1);
|
|
LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_POLARITY_FALLING);
|
|
LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_FILTER_FDIV1);
|
|
|
|
// Timer: channel 2 direct
|
|
LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_DIRECTTI);
|
|
LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
|
|
LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_POLARITY_RISING);
|
|
LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_FILTER_FDIV1);
|
|
|
|
// ISR setup
|
|
furi_hal_interrupt_set_timer_isr(TIM2, furi_hal_subghz_capture_ISR);
|
|
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
|
NVIC_EnableIRQ(TIM2_IRQn);
|
|
|
|
// Interrupts and channels
|
|
LL_TIM_EnableIT_CC1(TIM2);
|
|
LL_TIM_EnableIT_CC2(TIM2);
|
|
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
|
|
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
|
|
|
|
// Enable NVIC
|
|
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
|
NVIC_EnableIRQ(TIM2_IRQn);
|
|
|
|
// Start timer
|
|
LL_TIM_SetCounter(TIM2, 0);
|
|
LL_TIM_EnableCounter(TIM2);
|
|
|
|
// Switch to RX
|
|
furi_hal_subghz_rx();
|
|
}
|
|
|
|
void furi_hal_subghz_stop_async_rx() {
|
|
furi_assert(furi_hal_subghz_state == SubGhzStateAsyncRx);
|
|
furi_hal_subghz_state = SubGhzStateIdle;
|
|
|
|
// Shutdown radio
|
|
furi_hal_subghz_idle();
|
|
|
|
LL_TIM_DeInit(TIM2);
|
|
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
|
furi_hal_interrupt_set_timer_isr(TIM2, NULL);
|
|
|
|
hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
|
|
}
|
|
|
|
#define API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL (256)
|
|
#define API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF (API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL / 2)
|
|
#define API_HAL_SUBGHZ_ASYNC_TX_GUARD_TIME 333
|
|
|
|
typedef struct {
|
|
uint32_t* buffer;
|
|
bool flip_flop;
|
|
FuriHalSubGhzAsyncTxCallback callback;
|
|
void* callback_context;
|
|
} FuriHalSubGhzAsyncTx;
|
|
|
|
static FuriHalSubGhzAsyncTx furi_hal_subghz_async_tx = {0};
|
|
|
|
static void furi_hal_subghz_async_tx_refill(uint32_t* buffer, size_t samples) {
|
|
while(samples > 0) {
|
|
bool is_odd = samples % 2;
|
|
LevelDuration ld =
|
|
furi_hal_subghz_async_tx.callback(furi_hal_subghz_async_tx.callback_context);
|
|
if(level_duration_is_reset(ld)) {
|
|
// One more even sample required to end at low level
|
|
if(is_odd) {
|
|
*buffer = API_HAL_SUBGHZ_ASYNC_TX_GUARD_TIME;
|
|
buffer++;
|
|
samples--;
|
|
}
|
|
break;
|
|
} else {
|
|
// Inject guard time if level is incorrect
|
|
if(is_odd == level_duration_get_level(ld)) {
|
|
*buffer = API_HAL_SUBGHZ_ASYNC_TX_GUARD_TIME;
|
|
buffer++;
|
|
samples--;
|
|
}
|
|
|
|
uint32_t duration = level_duration_get_duration(ld);
|
|
assert(duration > 0);
|
|
*buffer = duration;
|
|
buffer++;
|
|
samples--;
|
|
}
|
|
}
|
|
|
|
memset(buffer, 0, samples * sizeof(uint32_t));
|
|
}
|
|
|
|
static void furi_hal_subghz_async_tx_dma_isr() {
|
|
furi_assert(furi_hal_subghz_state == SubGhzStateAsyncTx);
|
|
if(LL_DMA_IsActiveFlag_HT1(DMA1)) {
|
|
LL_DMA_ClearFlag_HT1(DMA1);
|
|
furi_hal_subghz_async_tx_refill(
|
|
furi_hal_subghz_async_tx.buffer, API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF);
|
|
}
|
|
if(LL_DMA_IsActiveFlag_TC1(DMA1)) {
|
|
LL_DMA_ClearFlag_TC1(DMA1);
|
|
furi_hal_subghz_async_tx_refill(
|
|
furi_hal_subghz_async_tx.buffer + API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF,
|
|
API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF);
|
|
}
|
|
}
|
|
|
|
static void furi_hal_subghz_async_tx_timer_isr() {
|
|
if(LL_TIM_IsActiveFlag_UPDATE(TIM2)) {
|
|
LL_TIM_ClearFlag_UPDATE(TIM2);
|
|
if(LL_TIM_GetAutoReload(TIM2) == 0) {
|
|
if(furi_hal_subghz_state == SubGhzStateAsyncTx) {
|
|
furi_hal_subghz_state = SubGhzStateAsyncTxLast;
|
|
} else {
|
|
furi_hal_subghz_state = SubGhzStateAsyncTxEnd;
|
|
LL_TIM_DisableCounter(TIM2);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void furi_hal_subghz_start_async_tx(FuriHalSubGhzAsyncTxCallback callback, void* context) {
|
|
furi_assert(furi_hal_subghz_state == SubGhzStateIdle);
|
|
furi_assert(callback);
|
|
|
|
furi_hal_subghz_async_tx.callback = callback;
|
|
furi_hal_subghz_async_tx.callback_context = context;
|
|
|
|
furi_hal_subghz_state = SubGhzStateAsyncTx;
|
|
|
|
furi_hal_subghz_async_tx.buffer =
|
|
furi_alloc(API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL * sizeof(uint32_t));
|
|
furi_hal_subghz_async_tx_refill(
|
|
furi_hal_subghz_async_tx.buffer, API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL);
|
|
|
|
// Connect CC1101_GD0 to TIM2 as output
|
|
hal_gpio_init_ex(
|
|
&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullDown, GpioSpeedLow, GpioAltFn1TIM2);
|
|
|
|
// Configure DMA
|
|
LL_DMA_InitTypeDef dma_config = {0};
|
|
dma_config.PeriphOrM2MSrcAddress = (uint32_t) & (TIM2->ARR);
|
|
dma_config.MemoryOrM2MDstAddress = (uint32_t)furi_hal_subghz_async_tx.buffer;
|
|
dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
|
|
dma_config.Mode = LL_DMA_MODE_CIRCULAR;
|
|
dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
|
|
dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
|
|
dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
|
|
dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
|
|
dma_config.NbData = API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL;
|
|
dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
|
|
dma_config.Priority = LL_DMA_MODE_NORMAL;
|
|
LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
|
|
furi_hal_interrupt_set_dma_channel_isr(
|
|
DMA1, LL_DMA_CHANNEL_1, furi_hal_subghz_async_tx_dma_isr);
|
|
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
|
|
LL_DMA_EnableIT_HT(DMA1, LL_DMA_CHANNEL_1);
|
|
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
|
|
|
|
// Configure TIM2
|
|
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
|
LL_TIM_InitTypeDef TIM_InitStruct = {0};
|
|
TIM_InitStruct.Prescaler = 64 - 1;
|
|
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
|
|
TIM_InitStruct.Autoreload = 1000;
|
|
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
|
|
LL_TIM_Init(TIM2, &TIM_InitStruct);
|
|
LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
|
|
LL_TIM_EnableARRPreload(TIM2);
|
|
|
|
// Configure TIM2 CH2
|
|
LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
|
|
TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;
|
|
TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
|
|
TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
|
|
TIM_OC_InitStruct.CompareValue = 0;
|
|
TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
|
|
LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct);
|
|
LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH2);
|
|
LL_TIM_DisableMasterSlaveMode(TIM2);
|
|
|
|
furi_hal_interrupt_set_timer_isr(TIM2, furi_hal_subghz_async_tx_timer_isr);
|
|
LL_TIM_EnableIT_UPDATE(TIM2);
|
|
LL_TIM_EnableDMAReq_UPDATE(TIM2);
|
|
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
|
|
|
|
// Start counter
|
|
LL_TIM_GenerateEvent_UPDATE(TIM2);
|
|
#ifdef FURI_HAL_SUBGHZ_TX_GPIO
|
|
hal_gpio_write(&FURI_HAL_SUBGHZ_TX_GPIO, true);
|
|
#endif
|
|
furi_hal_subghz_tx();
|
|
|
|
// Enable NVIC
|
|
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
|
NVIC_EnableIRQ(TIM2_IRQn);
|
|
|
|
LL_TIM_SetCounter(TIM2, 0);
|
|
LL_TIM_EnableCounter(TIM2);
|
|
}
|
|
|
|
bool furi_hal_subghz_is_async_tx_complete() {
|
|
return furi_hal_subghz_state == SubGhzStateAsyncTxEnd;
|
|
}
|
|
|
|
void furi_hal_subghz_stop_async_tx() {
|
|
furi_assert(
|
|
furi_hal_subghz_state == SubGhzStateAsyncTx ||
|
|
furi_hal_subghz_state == SubGhzStateAsyncTxLast ||
|
|
furi_hal_subghz_state == SubGhzStateAsyncTxEnd);
|
|
|
|
// Shutdown radio
|
|
furi_hal_subghz_idle();
|
|
#ifdef FURI_HAL_SUBGHZ_TX_GPIO
|
|
hal_gpio_write(&FURI_HAL_SUBGHZ_TX_GPIO, false);
|
|
#endif
|
|
|
|
// Deinitialize Timer
|
|
LL_TIM_DeInit(TIM2);
|
|
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
|
furi_hal_interrupt_set_timer_isr(TIM2, NULL);
|
|
|
|
// Deinitialize DMA
|
|
LL_DMA_DeInit(DMA1, LL_DMA_CHANNEL_1);
|
|
furi_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, NULL);
|
|
|
|
// Deinitialize GPIO
|
|
hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
|
|
|
|
free(furi_hal_subghz_async_tx.buffer);
|
|
|
|
furi_hal_subghz_state = SubGhzStateIdle;
|
|
}
|