mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-11-24 05:23:06 +00:00
317 lines
11 KiB
C
317 lines
11 KiB
C
#include <cc1101.h>
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/* ========================== DATA RATE SETTINGS ===============================
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*
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* This is how to configure registers MDMCFG3 and MDMCFG4.
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*
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* MDMCFG3 is the data rate mantissa, the exponent is in MDMCFG4,
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* last 4 bits of the register.
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*
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* The rate (assuming 26Mhz crystal) is calculated as follows:
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*
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* ((256+MDMCFG3)*(2^MDMCFG4:0..3bits)) / 2^28 * 26000000.
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*
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* For instance for the default values of MDMCFG3[0..3] (34) and MDMCFG4 (12):
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*
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* ((256+34)*(2^12))/(2^28)*26000000 = 115051.2688000000, that is 115KBaud
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*
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* ============================ BANDWIDTH FILTER ===============================
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*
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* Bandwidth filter setting:
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*
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* BW filter as just 16 possibilities depending on how the first nibble
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* (first 4 bits) of the MDMCFG4 bits are set. Instead of providing the
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* formula, it is simpler to show all the values of the nibble and the
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* corresponding bandwidth filter.
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*
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* 0 812khz
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* 1 650khz
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* 2 541khz
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* 3 464khz
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* 4 406khz
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* 5 325khz
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* 6 270khz
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* 7 232khz
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* 8 203khz
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* 9 162khz
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* a 135khz
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* b 116khz
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* c 102khz
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* d 82 khz
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* e 68 khz
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* f 58 khz
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*
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* ============================== FSK DEVIATION ================================
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*
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* FSK deviation is controlled by the DEVIATION register. In Ruby:
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*
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* dev = (26000000.0/2**17)*(8+(deviation&7))*(2**(deviation>>4&7))
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*
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* deviation&7 (last three bits) is the deviation mantissa, while
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* deviation>>4&7 (bits 6,5,4) are the exponent.
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*
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* Deviations values according to certain configuration of DEVIATION:
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*
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* 0x04 -> 2.380371 kHz
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* 0x24 -> 9.521484 kHz
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* 0x34 -> 19.042969 Khz
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* 0x40 -> 25.390625 Khz
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* 0x43 -> 34.912109 Khz
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* 0x45 -> 41.259765 Khz
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* 0x47 -> 47.607422 kHz
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*/
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/* 20 KBaud, 2FSK, 28.56 kHz deviation, 325 Khz bandwidth filter. */
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static uint8_t protoview_subghz_tpms1_fsk_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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{CC1101_PKTCTRL1, 0x04},
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// // Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x02},
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{CC1101_MDMCFG2,
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0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized). Other code reading TPMS uses GFSK, but should be the same when in RX mode.
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{CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud
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{CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz
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{CC1101_DEVIATN, 0x41}, // Deviation 28.56 kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0,
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0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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{CC1101_AGCCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
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{CC1101_FREND1, 0x56},
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/* End */
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{0, 0},
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/* CC1101 2FSK PATABLE. */
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{0xC0, 0},
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{0, 0},
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{0, 0},
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{0, 0}};
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/* This is like the default Flipper OOK 640Khz bandwidth preset, but
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* the bandwidth is changed to 10kBaud to accomodate TPMS frequency. */
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static const uint8_t protoview_subghz_tpms2_ook_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
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{CC1101_MDMCFG3, 0x93}, // Data rate is 10kBaud
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{CC1101_MDMCFG4, 0x18}, // Rx BW filter is 650.000kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0,
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0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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{CC1101_AGCCTRL1,
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0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
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{CC1101_FREND1, 0xB6}, //
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/* End */
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{0, 0},
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/* CC1101 OOK PATABLE. */
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{0, 0xC0},
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{0, 0},
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{0, 0},
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{0, 0}};
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/* GFSK 19k dev, 325 Khz filter, 20kBaud. Different AGI settings.
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* Works well with Toyota. */
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static uint8_t protoview_subghz_tpms3_gfsk_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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{CC1101_PKTCTRL1, 0x04},
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// // Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x02}, // 2 is the channel spacing exponet: not used
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{CC1101_MDMCFG2, 0x10}, // GFSK without any other check
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{CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud
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{CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz
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{CC1101_DEVIATN, 0x34}, // Deviation 19.04 Khz.
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0, 0x80},
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{CC1101_AGCCTRL1, 0x58},
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{CC1101_AGCCTRL2, 0x87},
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
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{CC1101_FREND1, 0x56},
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/* End */
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{0, 0},
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/* CC1101 2FSK PATABLE. */
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{0xC0, 0},
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{0, 0},
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{0, 0},
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{0, 0}};
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/* 40 KBaud, 2FSK, 28 kHz deviation, 270 Khz bandwidth filter. */
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static uint8_t protoview_subghz_40k_fsk_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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{CC1101_PKTCTRL1, 0x04},
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// // Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x02},
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{CC1101_MDMCFG2,
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0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized). Other code reading TPMS uses GFSK, but should be the same when in RX mode.
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{CC1101_MDMCFG3, 0x93}, // Data rate is 40kBaud
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{CC1101_MDMCFG4, 0x6A}, // 6 = BW filter 270kHz, A = Data rate exp
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{CC1101_DEVIATN, 0x41}, // Deviation 28kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0,
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0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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{CC1101_AGCCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
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{CC1101_FREND1, 0x56},
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/* End */
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{0, 0},
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/* CC1101 2FSK PATABLE. */
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{0xC0, 0},
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{0, 0},
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{0, 0},
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{0, 0}};
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/* This is like the default Flipper OOK 640Khz bandwidth preset, but
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* the bandwidth is changed to 40kBaud, in order to receive signals
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* with a pulse width ~25us/30us. */
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static const uint8_t protoview_subghz_40k_ook_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
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{CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
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{CC1101_MDMCFG3, 0x93}, // Data rate is 40kBaud
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{CC1101_MDMCFG4, 0x1A}, // Rx BW filter is 650.000kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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{CC1101_FOCCFG,
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCCTRL0,
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0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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{CC1101_AGCCTRL1,
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0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
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{CC1101_FREND1, 0xB6}, //
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/* End */
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{0, 0},
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/* CC1101 OOK PATABLE. */
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{0, 0xC0},
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{0, 0},
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{0, 0},
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{0, 0}};
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