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あく 418c0939a0
Guard RCC registers access with critical section (#854) 
* Core: critical section macros. FuriHal: guard rcc registers access with critical section, fix condition race.
* FuriHal: update documentation.

Co-authored-by: SG <who.just.the.doctor@gmail.com>
2021-12-01 01:07:17 +03:00
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f6 Guard RCC registers access with critical section (#854) 2021-12-01 01:07:17 +03:00
f7 Guard RCC registers access with critical section (#854) 2021-12-01 01:07:17 +03:00
furi-hal-include [FL-2060] FuriHal: SPI refactoring, flexible bus reconfiguration on fly, same design as i2c. (#853) 2021-11-30 15:09:43 +03:00