mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-11-23 04:53:08 +00:00
d92b0a82cc
"A long time ago in a galaxy far, far away...." we started NFC subsystem refactoring. Starring: - @gornekich - NFC refactoring project lead, architect, senior developer - @gsurkov - architect, senior developer - @RebornedBrain - senior developer Supporting roles: - @skotopes, @DrZlo13, @hedger - general architecture advisors, code review - @Astrrra, @doomwastaken, @Hellitron, @ImagineVagon333 - quality assurance Special thanks: @bettse, @pcunning, @nxv, @noproto, @AloneLiberty and everyone else who has been helping us all this time and contributing valuable knowledges, ideas and source code.
113 lines
4.9 KiB
C
113 lines
4.9 KiB
C
#pragma once
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#include "st25r3916_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ST25R3916_IRQ_MASK_ALL (uint32_t)(0xFFFFFFFFUL) /** All ST25R3916 interrupt sources */
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#define ST25R3916_IRQ_MASK_NONE (uint32_t)(0x00000000UL) /**No ST25R3916 interrupt source */
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/** Main interrupt register */
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#define ST25R3916_IRQ_MASK_OSC (uint32_t)(0x00000080U) /** ST25R3916 oscillator stable interrupt */
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#define ST25R3916_IRQ_MASK_FWL (uint32_t)(0x00000040U) /** ST25R3916 FIFO water level interrupt */
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#define ST25R3916_IRQ_MASK_RXS (uint32_t)(0x00000020U) /** ST25R3916 start of receive interrupt */
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#define ST25R3916_IRQ_MASK_RXE (uint32_t)(0x00000010U) /** ST25R3916 end of receive interrupt */
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#define ST25R3916_IRQ_MASK_TXE \
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(uint32_t)(0x00000008U) /** ST25R3916 end of transmission interrupt */
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#define ST25R3916_IRQ_MASK_COL (uint32_t)(0x00000004U) /** ST25R3916 bit collision interrupt */
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#define ST25R3916_IRQ_MASK_RX_REST \
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(uint32_t)(0x00000002U) /** ST25R3916 automatic reception restart interrupt */
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#define ST25R3916_IRQ_MASK_RFU (uint32_t)(0x00000001U) /** ST25R3916 RFU interrupt */
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/** Timer and NFC interrupt register */
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#define ST25R3916_IRQ_MASK_DCT \
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(uint32_t)(0x00008000U) /** ST25R3916 termination of direct command interrupt. */
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#define ST25R3916_IRQ_MASK_NRE \
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(uint32_t)(0x00004000U) /** ST25R3916 no-response timer expired interrupt */
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#define ST25R3916_IRQ_MASK_GPE \
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(uint32_t)(0x00002000U) /** ST25R3916 general purpose timer expired interrupt */
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#define ST25R3916_IRQ_MASK_EON (uint32_t)(0x00001000U) /** ST25R3916 external field on interrupt */
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#define ST25R3916_IRQ_MASK_EOF \
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(uint32_t)(0x00000800U) /** ST25R3916 external field off interrupt */
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#define ST25R3916_IRQ_MASK_CAC \
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(uint32_t)(0x00000400U) /** ST25R3916 collision during RF collision avoidance */
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#define ST25R3916_IRQ_MASK_CAT \
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(uint32_t)(0x00000200U) /** ST25R3916 minimum guard time expired interrupt */
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#define ST25R3916_IRQ_MASK_NFCT \
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(uint32_t)(0x00000100U) /** ST25R3916 initiator bit rate recognised interrupt */
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/** Error and wake-up interrupt register */
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#define ST25R3916_IRQ_MASK_CRC (uint32_t)(0x00800000U) /** ST25R3916 CRC error interrupt */
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#define ST25R3916_IRQ_MASK_PAR (uint32_t)(0x00400000U) /** ST25R3916 parity error interrupt */
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#define ST25R3916_IRQ_MASK_ERR2 \
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(uint32_t)(0x00200000U) /** ST25R3916 soft framing error interrupt */
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#define ST25R3916_IRQ_MASK_ERR1 \
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(uint32_t)(0x00100000U) /** ST25R3916 hard framing error interrupt */
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#define ST25R3916_IRQ_MASK_WT (uint32_t)(0x00080000U) /** ST25R3916 wake-up interrupt */
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#define ST25R3916_IRQ_MASK_WAM \
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(uint32_t)(0x00040000U) /** ST25R3916 wake-up due to amplitude interrupt */
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#define ST25R3916_IRQ_MASK_WPH \
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(uint32_t)(0x00020000U) /** ST25R3916 wake-up due to phase interrupt */
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#define ST25R3916_IRQ_MASK_WCAP \
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(uint32_t)(0x00010000U) /** ST25R3916 wake-up due to capacitance measurement */
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/** Passive Target Interrupt Register */
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#define ST25R3916_IRQ_MASK_PPON2 \
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(uint32_t)(0x80000000U) /** ST25R3916 PPON2 Field on waiting Timer interrupt */
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#define ST25R3916_IRQ_MASK_SL_WL \
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(uint32_t)(0x40000000U) /** ST25R3916 Passive target slot number water level interrupt */
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#define ST25R3916_IRQ_MASK_APON \
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(uint32_t)(0x20000000U) /** ST25R3916 Anticollision done and Field On interrupt */
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#define ST25R3916_IRQ_MASK_RXE_PTA \
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(uint32_t)(0x10000000U) /** ST25R3916 RXE with an automatic response interrupt */
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#define ST25R3916_IRQ_MASK_WU_F \
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(uint32_t)(0x08000000U) /** ST25R3916 212/424b/s Passive target interrupt: Active */
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#define ST25R3916_IRQ_MASK_RFU2 (uint32_t)(0x04000000U) /** ST25R3916 RFU2 interrupt */
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#define ST25R3916_IRQ_MASK_WU_A_X \
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(uint32_t)(0x02000000U) /** ST25R3916 106kb/s Passive target state interrupt: Active* */
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#define ST25R3916_IRQ_MASK_WU_A \
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(uint32_t)(0x01000000U) /** ST25R3916 106kb/s Passive target state interrupt: Active */
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/** Mask st25r3916 interrupts
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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* @param mask - mask of interrupts to be disabled
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*/
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void st25r3916_mask_irq(FuriHalSpiBusHandle* handle, uint32_t mask);
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/** Get st25r3916 interrupts
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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*
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* @return received interrupts
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*/
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uint32_t st25r3916_get_irq(FuriHalSpiBusHandle* handle);
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/** Write FIFO
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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* @param buff - buffer to write to FIFO
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* @param bits - number of bits to write
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*/
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void st25r3916_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* buff, size_t bits);
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/** Read FIFO
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*
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* @param handle - pointer to FuriHalSpiBusHandle instance
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* @param buff - buffer to read from FIFO
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* @param buff_size - buffer size n bytes
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* @param buff_bits - pointer to number of bits read
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*
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* @return true if read success, false otherwise
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*/
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bool st25r3916_read_fifo(
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FuriHalSpiBusHandle* handle,
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uint8_t* buff,
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size_t buff_size,
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size_t* buff_bits);
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#ifdef __cplusplus
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}
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#endif
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