mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-11-27 23:10:22 +00:00
734820c137
* Targets: add F6 * F6: Update linker script for use with internal storage * F6: synchronize with F5, add all changes arriving in V9 board, update cube project. Github workflow: add multi-target build, add F6 to build targets. * CI: fix full assembly * CI: better artifact naming scheme * CI: fix artifacts wildcard * F6: Swap C10 - A15, vibro and sdcard detect pins
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
#include "cmsis_os.h"
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#include "api-hal-task.h"
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//-----------------------------cmsis_os2.c-------------------------------
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// helpers to get isr context
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// get arch
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#ifndef __ARM_ARCH_6M__
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#define __ARM_ARCH_6M__ 0
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#endif
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#ifndef __ARM_ARCH_7M__
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#define __ARM_ARCH_7M__ 0
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#endif
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#ifndef __ARM_ARCH_7EM__
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#define __ARM_ARCH_7EM__ 0
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#endif
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#ifndef __ARM_ARCH_8M_MAIN__
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#define __ARM_ARCH_8M_MAIN__ 0
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#endif
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#ifndef __ARM_ARCH_7A__
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#define __ARM_ARCH_7A__ 0
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#endif
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// get masks
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#if((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M_MAIN__ == 1U))
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#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
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#elif(__ARM_ARCH_6M__ == 1U)
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#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
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#elif(__ARM_ARCH_7A__ == 1U)
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/* CPSR mask bits */
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#define CPSR_MASKBIT_I 0x80U
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#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U)
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#else
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#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
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#endif
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// get is irq mode
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#if(__ARM_ARCH_7A__ == 1U)
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/* CPSR mode bitmasks */
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#define CPSR_MODE_USER 0x10U
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#define CPSR_MODE_SYSTEM 0x1FU
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#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM))
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#else
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#define IS_IRQ_MODE() (__get_IPSR() != 0U)
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#endif
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// added osKernelGetState(), because KernelState is a static var
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#define IS_IRQ() (IS_IRQ_MODE() || (IS_IRQ_MASKED() && (osKernelGetState() == osKernelRunning)))
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//-------------------------end of cmsis_os2.c----------------------------
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bool task_is_isr_context(void) {
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return IS_IRQ();
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}
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