mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-12-12 06:02:28 +00:00
482 lines
No EOL
13 KiB
C
482 lines
No EOL
13 KiB
C
#include "cc1101_configs.h"
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#include <cc1101_regs.h>
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const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* FIFO and internals */
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CC1101_FIFOTHR,
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0x47, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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CC1101_MDMCFG0,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG1,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG2,
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0x30, // Format ASK/OOK, No preamble/sync
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CC1101_MDMCFG3,
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0x32, // Data rate is 3.79372 kBaud
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CC1101_MDMCFG4,
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0x67, // Rx BW filter is 270.833333kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x18, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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CC1101_AGCCTRL0,
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0x40, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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CC1101_AGCCTRL1,
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0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x03, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x11, // Adjusts current TX LO buffer + high is PATABLE[1]
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CC1101_FREND1,
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0xB6, //
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/* End load reg */
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0,
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0,
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//ook_async_patable[8]
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0x00,
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0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* FIFO and internals */
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CC1101_FIFOTHR,
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0x07, // The only important bit is ADC_RETENTION
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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CC1101_MDMCFG0,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG1,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG2,
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0x30, // Format ASK/OOK, No preamble/sync
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CC1101_MDMCFG3,
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0x32, // Data rate is 3.79372 kBaud
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CC1101_MDMCFG4,
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0x17, // Rx BW filter is 650.000kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x18, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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// CC1101_AGCTRL0,0x40, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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// CC1101_AGCTRL1,0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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// CC1101_AGCCTRL2, 0x03, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
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CC1101_AGCCTRL0,
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0x91, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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CC1101_AGCCTRL1,
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0x0, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x11, // Adjusts current TX LO buffer + high is PATABLE[1]
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CC1101_FREND1,
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0xB6, //
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/* End load reg */
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0,
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0,
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//ook_async_patable[8]
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0x00,
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0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[] = {
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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CC1101_PKTCTRL1,
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0x04,
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// // Modem Configuration
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CC1101_MDMCFG0,
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0x00,
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CC1101_MDMCFG1,
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0x02,
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CC1101_MDMCFG2,
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0x04, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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CC1101_MDMCFG3,
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0x83, // Data rate is 4.79794 kBaud
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CC1101_MDMCFG4,
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0x67, //Rx BW filter is 270.833333 kHz
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CC1101_DEVIATN,
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0x04, //Deviation 2.380371 kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x16, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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CC1101_AGCCTRL0,
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0x91, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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CC1101_AGCCTRL1,
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0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x10, // Adjusts current TX LO buffer
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CC1101_FREND1,
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0x56,
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/* End load reg */
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0,
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0,
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// 2fsk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[] = {
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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CC1101_PKTCTRL1,
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0x04,
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// // Modem Configuration
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CC1101_MDMCFG0,
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0x00,
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CC1101_MDMCFG1,
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0x02,
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CC1101_MDMCFG2,
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0x04, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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CC1101_MDMCFG3,
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0x83, // Data rate is 4.79794 kBaud
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CC1101_MDMCFG4,
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0x67, //Rx BW filter is 270.833333 kHz
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CC1101_DEVIATN,
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0x47, //Deviation 47.60742 kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x16, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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CC1101_AGCCTRL0,
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0x91, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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CC1101_AGCCTRL1,
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0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x10, // Adjusts current TX LO buffer
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CC1101_FREND1,
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0x56,
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/* End load reg */
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0,
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0,
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// 2fsk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[] = {
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x06,
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CC1101_FIFOTHR,
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0x07, // The only important bit is ADC_RETENTION
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CC1101_SYNC1,
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0x46,
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CC1101_SYNC0,
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0x4C,
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CC1101_ADDR,
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0x00,
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CC1101_PKTLEN,
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0x00,
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CC1101_CHANNR,
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0x00,
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CC1101_PKTCTRL0,
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0x05,
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CC1101_FSCTRL0,
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0x23,
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CC1101_FSCTRL1,
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0x06,
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CC1101_MDMCFG0,
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0xF8,
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CC1101_MDMCFG1,
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0x22,
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CC1101_MDMCFG2,
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0x72,
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CC1101_MDMCFG3,
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0xF8,
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CC1101_MDMCFG4,
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0x5B,
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CC1101_DEVIATN,
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0x47,
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CC1101_MCSM0,
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0x18,
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CC1101_FOCCFG,
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0x16,
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CC1101_AGCCTRL0,
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0xB2,
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CC1101_AGCCTRL1,
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0x00,
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CC1101_AGCCTRL2,
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0xC7,
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CC1101_FREND0,
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0x10,
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CC1101_FREND1,
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0x56,
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CC1101_BSCFG,
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0x1C,
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CC1101_FSTEST,
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0x59,
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/* End load reg */
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0,
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0,
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// msk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[] = {
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CC1101_IOCFG0,
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0x06, //GDO0 Output Pin Configuration
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CC1101_FIFOTHR,
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0x47, //RX FIFO and TX FIFO Thresholds
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//1 : CRC calculation in TX and CRC check in RX enabled,
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//1 : Variable packet length mode. Packet length configured by the first byte after sync word
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CC1101_PKTCTRL0,
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0x05,
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CC1101_FSCTRL1,
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0x06, //Frequency Synthesizer Control
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CC1101_SYNC1,
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0x46,
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CC1101_SYNC0,
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0x4C,
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CC1101_ADDR,
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0x00,
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CC1101_PKTLEN,
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0x00,
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CC1101_MDMCFG4,
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0xC8, //Modem Configuration 9.99
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CC1101_MDMCFG3,
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0x93, //Modem Configuration
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CC1101_MDMCFG2,
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0x12, // 2: 16/16 sync word bits detected
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CC1101_DEVIATN,
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0x34, //Deviation = 19.042969
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CC1101_MCSM0,
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0x18, //Main Radio Control State Machine Configuration
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CC1101_FOCCFG,
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0x16, //Frequency Offset Compensation Configuration
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CC1101_AGCCTRL2,
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0x43, //AGC Control
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CC1101_AGCCTRL1,
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0x40,
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CC1101_AGCCTRL0,
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0x91,
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CC1101_WORCTRL,
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0xFB, //Wake On Radio Control
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/* End load reg */
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0,
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0,
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// gfsk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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// Shpargalka
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// const uint8_t subghz_device_cc1101_preset_ook_async_patable[8] = {
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// 0x00,
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// 0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00};
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// const uint8_t subghz_device_cc1101_preset_ook_async_patable_au[8] = {
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// 0x00,
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// 0x37, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00};
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// const uint8_t subghz_device_cc1101_preset_2fsk_async_patable[8] = {
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// 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00};
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// const uint8_t subghz_device_cc1101_preset_msk_async_patable[8] = {
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// 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00};
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// const uint8_t subghz_device_cc1101_preset_gfsk_async_patable[8] = {
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// 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00,
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// 0x00};
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