mirror of
https://github.com/DarkFlippers/unleashed-firmware
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1016 lines
22 KiB
C
1016 lines
22 KiB
C
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#include <furi.h>
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#include <stdlib.h>
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#include "adi.h"
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#include "swd_probe_app.h"
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/* https://github.com/openocd-org/openocd/blob/master/src/target/arm_adi_v5.c */
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/*
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static const char* class_description[16] = {
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[0x0] = "Generic verification component",
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[0x1] = "(ROM Table)",
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[0x2] = "Reserved",
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[0x3] = "Reserved",
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[0x4] = "Reserved",
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[0x5] = "Reserved",
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[0x6] = "Reserved",
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[0x7] = "Reserved",
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[0x8] = "Reserved",
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[0x9] = "CoreSight component",
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[0xA] = "Reserved",
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[0xB] = "Peripheral Test Block",
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[0xC] = "Reserved",
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[0xD] = "OptimoDE DESS",
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[0xE] = "Generic IP component",
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[0xF] = "CoreLink, PrimeCell or System component",
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};
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*/
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static const struct {
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uint32_t arch_id;
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const char* description;
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} class0x9_devarch[] = {
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/* keep same unsorted order as in ARM IHI0029E */
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{ARCH_ID(ARM_ID, 0x0A00), "RAS architecture"},
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{ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture"},
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{ARCH_ID(ARM_ID, 0x1A02), "DWT architecture"},
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{ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture"},
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{ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)"},
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{ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)"},
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{ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling"},
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{ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture"},
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{ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture"},
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{ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)"},
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{ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)"},
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{ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)"},
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{ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture"},
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{ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture"},
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{ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture"},
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{ARCH_ID(ARM_ID, 0x0A31), "Basic trace router"},
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{ARCH_ID(ARM_ID, 0x0A37), "Power requestor"},
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{ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture"},
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{ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture"},
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{ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture"},
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{ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture"},
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{ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture"},
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};
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/* Part number interpretations are from Cortex
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* core specs, the CoreSight components TRM
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* (ARM DDI 0314H), CoreSight System Design
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* Guide (ARM DGI 0012D) and ETM specs; also
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* from chip observation (e.g. TI SDTI).
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*/
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static const struct dap_part_nums {
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uint16_t designer_id;
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uint16_t part_num;
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const char* type;
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const char* full;
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} dap_part_nums[] = {
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{
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ARM_ID,
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0x000,
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"Cortex-M3 SCS",
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"(System Control Space)",
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},
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{
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ARM_ID,
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0x001,
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"Cortex-M3 ITM",
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"(Instrumentation Trace Module)",
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},
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{
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ARM_ID,
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0x002,
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"Cortex-M3 DWT",
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"(Data Watchpoint and Trace)",
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},
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{
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ARM_ID,
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0x003,
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"Cortex-M3 FPB",
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"(Flash Patch and Breakpoint)",
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},
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{
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ARM_ID,
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0x008,
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"Cortex-M0 SCS",
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"(System Control Space)",
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},
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{
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ARM_ID,
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0x00a,
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"Cortex-M0 DWT",
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"(Data Watchpoint and Trace)",
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},
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{
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ARM_ID,
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0x00b,
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"Cortex-M0 BPU",
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"(Breakpoint Unit)",
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},
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{
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ARM_ID,
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0x00c,
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"Cortex-M4 SCS",
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"(System Control Space)",
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},
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{
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ARM_ID,
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0x00d,
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"CoreSight ETM11",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x00e,
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"Cortex-M7 FPB",
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"(Flash Patch and Breakpoint)",
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},
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{
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ARM_ID,
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0x193,
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"SoC-600 TSGEN",
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"(Timestamp Generator)",
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},
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{
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ARM_ID,
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0x470,
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"Cortex-M1 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x471,
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"Cortex-M0 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x490,
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"Cortex-A15 GIC",
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"(Generic Interrupt Controller)",
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},
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{
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ARM_ID,
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0x492,
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"Cortex-R52 GICD",
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"(Distributor)",
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},
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{
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ARM_ID,
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0x493,
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"Cortex-R52 GICR",
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"(Redistributor)",
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},
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{
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ARM_ID,
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0x4a1,
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"Cortex-A53 ROM",
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"(v8 Memory Map ROM Table)",
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},
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{
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ARM_ID,
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0x4a2,
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"Cortex-A57 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4a3,
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"Cortex-A53 ROM",
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"(v7 Memory Map ROM Table)",
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},
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{
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ARM_ID,
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0x4a4,
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"Cortex-A72 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4a9,
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"Cortex-A9 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4aa,
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"Cortex-A35 ROM",
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"(v8 Memory Map ROM Table)",
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},
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{
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ARM_ID,
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0x4af,
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"Cortex-A15 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4b5,
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"Cortex-R5 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4b8,
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"Cortex-R52 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4c0,
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"Cortex-M0+ ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4c3,
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"Cortex-M3 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4c4,
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"Cortex-M4 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4c7,
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"Cortex-M7 PPB ROM",
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"(Private Peripheral Bus ROM Table)",
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},
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{
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ARM_ID,
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0x4c8,
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"Cortex-M7 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x4e0,
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"Cortex-A35 ROM",
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"(v7 Memory Map ROM Table)",
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},
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{
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ARM_ID,
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0x4e4,
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"Cortex-A76 ROM",
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"(ROM Table)",
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},
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{
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ARM_ID,
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0x906,
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"CoreSight CTI",
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"(Cross Trigger)",
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},
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{
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ARM_ID,
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0x907,
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"CoreSight ETB",
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"(Trace Buffer)",
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},
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{
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ARM_ID,
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0x908,
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"CoreSight CSTF",
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"(Trace Funnel)",
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},
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{
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ARM_ID,
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0x909,
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"CoreSight ATBR",
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"(Advanced Trace Bus Replicator)",
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},
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{
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ARM_ID,
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0x910,
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"CoreSight ETM9",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x912,
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"CoreSight TPIU",
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"(Trace Port Interface Unit)",
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},
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{
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ARM_ID,
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0x913,
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"CoreSight ITM",
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"(Instrumentation Trace Macrocell)",
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},
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{
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ARM_ID,
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0x914,
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"CoreSight SWO",
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"(Single Wire Output)",
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},
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{
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ARM_ID,
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0x917,
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"CoreSight HTM",
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"(AHB Trace Macrocell)",
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},
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{
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ARM_ID,
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0x920,
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"CoreSight ETM11",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x921,
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"Cortex-A8 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x922,
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"Cortex-A8 CTI",
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"(Cross Trigger)",
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},
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{
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ARM_ID,
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0x923,
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"Cortex-M3 TPIU",
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"(Trace Port Interface Unit)",
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},
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{
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ARM_ID,
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0x924,
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"Cortex-M3 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x925,
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"Cortex-M4 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x930,
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"Cortex-R4 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x931,
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"Cortex-R5 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x932,
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"CoreSight MTB-M0+",
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"(Micro Trace Buffer)",
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},
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{
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ARM_ID,
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0x941,
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"CoreSight TPIU-Lite",
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"(Trace Port Interface Unit)",
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},
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{
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ARM_ID,
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0x950,
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"Cortex-A9 PTM",
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"(Program Trace Macrocell)",
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},
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{
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ARM_ID,
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0x955,
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"Cortex-A5 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x95a,
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"Cortex-A72 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x95b,
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"Cortex-A17 PTM",
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"(Program Trace Macrocell)",
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},
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{
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ARM_ID,
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0x95d,
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"Cortex-A53 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x95e,
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"Cortex-A57 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x95f,
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"Cortex-A15 PTM",
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"(Program Trace Macrocell)",
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},
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{
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ARM_ID,
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0x961,
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"CoreSight TMC",
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"(Trace Memory Controller)",
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},
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{
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ARM_ID,
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0x962,
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"CoreSight STM",
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"(System Trace Macrocell)",
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},
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{
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ARM_ID,
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0x975,
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"Cortex-M7 ETM",
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"(Embedded Trace)",
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},
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{
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ARM_ID,
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0x9a0,
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"CoreSight PMU",
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"(Performance Monitoring Unit)",
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},
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{
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ARM_ID,
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0x9a1,
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"Cortex-M4 TPIU",
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"(Trace Port Interface Unit)",
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},
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{
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ARM_ID,
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0x9a4,
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"CoreSight GPR",
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"(Granular Power Requester)",
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},
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{
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ARM_ID,
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0x9a5,
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"Cortex-A5 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9a7,
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"Cortex-A7 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9a8,
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"Cortex-A53 CTI",
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"(Cross Trigger)",
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},
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{
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ARM_ID,
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0x9a9,
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"Cortex-M7 TPIU",
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"(Trace Port Interface Unit)",
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},
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{
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ARM_ID,
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0x9ae,
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"Cortex-A17 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9af,
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"Cortex-A15 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9b6,
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"Cortex-R52 PMU/CTI/ETM",
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"(Performance Monitor Unit/Cross Trigger/ETM)",
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},
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{
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ARM_ID,
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0x9b7,
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"Cortex-R7 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9d3,
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"Cortex-A53 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9d7,
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"Cortex-A57 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9d8,
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"Cortex-A72 PMU",
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"(Performance Monitor Unit)",
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},
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{
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ARM_ID,
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0x9da,
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"Cortex-A35 PMU/CTI/ETM",
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"(Performance Monitor Unit/Cross Trigger/ETM)",
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},
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{
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ARM_ID,
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0x9e2,
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"SoC-600 APB-AP",
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"(APB4 Memory Access Port)",
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},
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{
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ARM_ID,
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0x9e3,
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"SoC-600 AHB-AP",
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"(AHB5 Memory Access Port)",
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},
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{
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ARM_ID,
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0x9e4,
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"SoC-600 AXI-AP",
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"(AXI Memory Access Port)",
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},
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{
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ARM_ID,
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0x9e5,
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"SoC-600 APv1 Adapter",
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"(Access Port v1 Adapter)",
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},
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{
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ARM_ID,
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0x9e6,
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"SoC-600 JTAG-AP",
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"(JTAG Access Port)",
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},
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{
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ARM_ID,
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0x9e7,
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"SoC-600 TPIU",
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"(Trace Port Interface Unit)",
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},
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{
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ARM_ID,
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0x9e8,
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"SoC-600 TMC ETR/ETS",
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"(Embedded Trace Router/Streamer)",
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},
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{
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ARM_ID,
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0x9e9,
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"SoC-600 TMC ETB",
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"(Embedded Trace Buffer)",
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},
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{
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ARM_ID,
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0x9ea,
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"SoC-600 TMC ETF",
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"(Embedded Trace FIFO)",
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},
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{
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ARM_ID,
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0x9eb,
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"SoC-600 ATB Funnel",
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"(Trace Funnel)",
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},
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{
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ARM_ID,
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0x9ec,
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"SoC-600 ATB Replicator",
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"(Trace Replicator)",
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},
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{
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ARM_ID,
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0x9ed,
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"SoC-600 CTI",
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"(Cross Trigger)",
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},
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{
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ARM_ID,
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0x9ee,
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"SoC-600 CATU",
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"(Address Translation Unit)",
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},
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{
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ARM_ID,
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0xc05,
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"Cortex-A5 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc07,
|
|
"Cortex-A7 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc08,
|
|
"Cortex-A8 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc09,
|
|
"Cortex-A9 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc0e,
|
|
"Cortex-A17 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc0f,
|
|
"Cortex-A15 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc14,
|
|
"Cortex-R4 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc15,
|
|
"Cortex-R5 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xc17,
|
|
"Cortex-R7 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd03,
|
|
"Cortex-A53 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd04,
|
|
"Cortex-A35 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd07,
|
|
"Cortex-A57 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd08,
|
|
"Cortex-A72 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd0b,
|
|
"Cortex-A76 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd0c,
|
|
"Neoverse N1",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd13,
|
|
"Cortex-R52 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
ARM_ID,
|
|
0xd49,
|
|
"Neoverse N2",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
0x017,
|
|
0x120,
|
|
"TI SDTI",
|
|
"(System Debug Trace Interface)",
|
|
}, /* from OMAP3 memmap */
|
|
{
|
|
0x017,
|
|
0x343,
|
|
"TI DAPCTL",
|
|
"",
|
|
}, /* from OMAP3 memmap */
|
|
{0x017, 0x9af, "MSP432 ROM", "(ROM Table)"},
|
|
{0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)"},
|
|
{0x041, 0x1db, "XMC4500 ROM", "(ROM Table)"},
|
|
{0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)"},
|
|
{0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)"},
|
|
{
|
|
0x065,
|
|
0x000,
|
|
"SHARC+/Blackfin+",
|
|
"",
|
|
},
|
|
{
|
|
0x070,
|
|
0x440,
|
|
"Qualcomm QDSS Component v1",
|
|
"(Qualcomm Designed CoreSight Component v1)",
|
|
},
|
|
{
|
|
0x0bf,
|
|
0x100,
|
|
"Brahma-B53 Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
0x0bf,
|
|
0x9d3,
|
|
"Brahma-B53 PMU",
|
|
"(Performance Monitor Unit)",
|
|
},
|
|
{
|
|
0x0bf,
|
|
0x4a1,
|
|
"Brahma-B53 ROM",
|
|
"(ROM Table)",
|
|
},
|
|
{
|
|
0x0bf,
|
|
0x721,
|
|
"Brahma-B53 ROM",
|
|
"(ROM Table)",
|
|
},
|
|
{
|
|
0x1eb,
|
|
0x181,
|
|
"Tegra 186 ROM",
|
|
"(ROM Table)",
|
|
},
|
|
{
|
|
0x1eb,
|
|
0x202,
|
|
"Denver ETM",
|
|
"(Denver Embedded Trace)",
|
|
},
|
|
{
|
|
0x1eb,
|
|
0x211,
|
|
"Tegra 210 ROM",
|
|
"(ROM Table)",
|
|
},
|
|
{
|
|
0x1eb,
|
|
0x302,
|
|
"Denver Debug",
|
|
"(Debug Unit)",
|
|
},
|
|
{
|
|
0x1eb,
|
|
0x402,
|
|
"Denver PMU",
|
|
"(Performance Monitor Unit)",
|
|
},
|
|
{0x20, 0x410, "STM32F10 (med)", "(ROM Table)"},
|
|
{0x20, 0x411, "STM32F2", "(ROM Table)"},
|
|
{0x20, 0x412, "STM32F10 (low)", "(ROM Table)"},
|
|
{0x20, 0x413, "STM32F40/41", "(ROM Table)"},
|
|
{0x20, 0x414, "STM32F10 (high)", "(ROM Table)"},
|
|
{0x20, 0x415, "STM32L47/48", "(ROM Table)"},
|
|
{0x20, 0x416, "STM32L1xxx6/8/B", "(ROM Table)"},
|
|
{0x20, 0x417, "STM32L05/06", "(ROM Table)"},
|
|
{0x20, 0x418, "STM32F105xx/107", "(ROM Table)"},
|
|
{0x20, 0x419, "STM32F42/43", "(ROM Table)"},
|
|
{0x20, 0x420, "STM32F10 (med)", "(ROM Table)"},
|
|
{0x20, 0x421, "STM32F446xx", "(ROM Table)"},
|
|
{0x20, 0x422, "STM32FF358/02/03", "(ROM Table)"},
|
|
{0x20, 0x423, "STM32F401xB/C", "(ROM Table)"},
|
|
{0x20, 0x425, "STM32L031/41", "(ROM Table)"},
|
|
{0x20, 0x427, "STM32L1xxxC", "(ROM Table)"},
|
|
{0x20, 0x428, "STM32F10 (high)", "(ROM Table)"},
|
|
{0x20, 0x429, "STM32L1xxx6A/8A/BA", "(ROM Table)"},
|
|
{0x20, 0x430, "STM32F10 (xl)", "(ROM Table)"},
|
|
{0x20, 0x431, "STM32F411xx", "(ROM Table)"},
|
|
{0x20, 0x432, "STM32F373/8", "(ROM Table)"},
|
|
{0x20, 0x433, "STM32F401xD/E", "(ROM Table)"},
|
|
{0x20, 0x434, "STM32F469/79", "(ROM Table)"},
|
|
{0x20, 0x435, "STM32L43/44", "(ROM Table)"},
|
|
{0x20, 0x436, "STM32L1xxxD", "(ROM Table)"},
|
|
{0x20, 0x437, "STM32L1xxxE", "(ROM Table)"},
|
|
{0x20, 0x438, "STM32F303/34/28", "(ROM Table)"},
|
|
{0x20, 0x439, "STM32F301/02/18 ", "(ROM Table)"},
|
|
{0x20, 0x440, "STM32F03/5", "(ROM Table)"},
|
|
{0x20, 0x441, "STM32F412xx", "(ROM Table)"},
|
|
{0x20, 0x442, "STM32F03/9", "(ROM Table)"},
|
|
{0x20, 0x444, "STM32F03xx4", "(ROM Table)"},
|
|
{0x20, 0x445, "STM32F04/7", "(ROM Table)"},
|
|
{0x20, 0x446, "STM32F302/03/98", "(ROM Table)"},
|
|
{0x20, 0x447, "STM32L07/08", "(ROM Table)"},
|
|
{0x20, 0x448, "STM32F070/1/2", "(ROM Table)"},
|
|
{0x20, 0x449, "STM32F74/5", "(ROM Table)"},
|
|
{0x20, 0x450, "STM32H74/5", "(ROM Table)"},
|
|
{0x20, 0x451, "STM32F76/7", "(ROM Table)"},
|
|
{0x20, 0x452, "STM32F72/3", "(ROM Table)"},
|
|
{0x20, 0x457, "STM32L01/2", "(ROM Table)"},
|
|
{0x20, 0x458, "STM32F410xx", "(ROM Table)"},
|
|
{0x20, 0x460, "STM32G07/8", "(ROM Table)"},
|
|
{0x20, 0x461, "STM32L496/A6", "(ROM Table)"},
|
|
{0x20, 0x462, "STM32L45/46", "(ROM Table)"},
|
|
{0x20, 0x463, "STM32F413/23", "(ROM Table)"},
|
|
{0x20, 0x464, "STM32L412/22", "(ROM Table)"},
|
|
{0x20, 0x466, "STM32G03/04", "(ROM Table)"},
|
|
{0x20, 0x468, "STM32G431/41", "(ROM Table)"},
|
|
{0x20, 0x469, "STM32G47/48", "(ROM Table)"},
|
|
{0x20, 0x470, "STM32L4R/S", "(ROM Table)"},
|
|
{0x20, 0x471, "STM32L4P5/Q5", "(ROM Table)"},
|
|
{0x20, 0x479, "STM32G491xx", "(ROM Table)"},
|
|
{0x20, 0x480, "STM32H7A/B", "(ROM Table)"},
|
|
{0x20, 0x495, "STM32WB50/55", "(ROM Table)"},
|
|
{0x20, 0x497, "STM32WLE5xx", "(ROM Table)"}};
|
|
|
|
const char* adi_devarch_desc(uint32_t devarch) {
|
|
if(!(devarch & ARM_CS_C9_DEVARCH_PRESENT)) {
|
|
return "not present";
|
|
}
|
|
|
|
for(unsigned int i = 0; i < ARRAY_SIZE(class0x9_devarch); i++) {
|
|
if((devarch & DEVARCH_ID_MASK) == class0x9_devarch[i].arch_id) {
|
|
return class0x9_devarch[i].description;
|
|
}
|
|
}
|
|
|
|
return "unknown";
|
|
}
|
|
|
|
const struct dap_part_nums* adi_part_num(unsigned int des, unsigned int part) {
|
|
static char buf[32];
|
|
static struct dap_part_nums unknown = {
|
|
.type = "Unrecognized",
|
|
.full = "",
|
|
};
|
|
|
|
for(unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++) {
|
|
if(dap_part_nums[i].designer_id == des && dap_part_nums[i].part_num == part) {
|
|
return &dap_part_nums[i];
|
|
}
|
|
}
|
|
|
|
snprintf(buf, sizeof(buf), "D:%x P:%x", des, part);
|
|
unknown.full = buf;
|
|
|
|
return &unknown;
|
|
}
|
|
|
|
bool adi_get_pidr(AppFSM* const ctx, uint32_t base, pidr_data_t* data) {
|
|
uint32_t pidrs[7];
|
|
uint32_t offsets[] = {0xFE0, 0xFE4, 0xFE8, 0xFEC, 0xFD0, 0xFD4, 0xFD8, 0xFDC};
|
|
|
|
furi_mutex_acquire(ctx->swd_mutex, FuriWaitForever);
|
|
for(size_t pos = 0; pos < COUNT(pidrs); pos++) {
|
|
uint8_t ret = swd_read_memory(ctx, ctx->ap_pos, base + offsets[pos], &pidrs[pos]);
|
|
if(ret != 1) {
|
|
DBGS("Read failed");
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
return false;
|
|
}
|
|
}
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
|
|
data->designer = ((pidrs[4] & 0x0F) << 7) | ((pidrs[2] & 0x07) << 4) |
|
|
((pidrs[1] >> 4) & 0x0F);
|
|
data->part = (pidrs[0] & 0xFF) | ((pidrs[1] & 0x0F) << 8);
|
|
data->revand = ((pidrs[3] >> 4) & 0x0F);
|
|
data->cmod = (pidrs[3] & 0x0F);
|
|
data->revision = ((pidrs[2] >> 4) & 0x0F);
|
|
data->size = ((pidrs[2] >> 4) & 0x0F);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool adi_get_class(AppFSM* const ctx, uint32_t base, uint8_t* class) {
|
|
uint32_t cidrs[4];
|
|
uint32_t offsets[] = {0xFF0, 0xFF4, 0xFF8, 0xFFC};
|
|
|
|
furi_mutex_acquire(ctx->swd_mutex, FuriWaitForever);
|
|
for(size_t pos = 0; pos < COUNT(cidrs); pos++) {
|
|
uint8_t ret = swd_read_memory(ctx, ctx->ap_pos, base + offsets[pos], &cidrs[pos]);
|
|
if(ret != 1) {
|
|
DBGS("Read failed");
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
return false;
|
|
}
|
|
}
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
|
|
if((cidrs[0] & 0xFF) != 0x0D) {
|
|
return false;
|
|
}
|
|
if((cidrs[1] & 0x0F) != 0x00) {
|
|
return false;
|
|
}
|
|
if((cidrs[2] & 0xFF) != 0x05) {
|
|
return false;
|
|
}
|
|
if((cidrs[3] & 0xFF) != 0xB1) {
|
|
return false;
|
|
}
|
|
|
|
*class = ((cidrs[1] >> 4) & 0x0F);
|
|
|
|
return true;
|
|
}
|
|
|
|
const char* adi_romtable_type(AppFSM* const ctx, uint32_t base) {
|
|
pidr_data_t data;
|
|
|
|
if(!adi_get_pidr(ctx, base, &data)) {
|
|
return "fail";
|
|
}
|
|
const struct dap_part_nums* info = adi_part_num(data.designer, data.part);
|
|
|
|
return info->type;
|
|
}
|
|
|
|
const char* adi_romtable_full(AppFSM* const ctx, uint32_t base) {
|
|
pidr_data_t data;
|
|
|
|
if(!adi_get_pidr(ctx, base, &data)) {
|
|
return "fail";
|
|
}
|
|
const struct dap_part_nums* info = adi_part_num(data.designer, data.part);
|
|
|
|
return info->full;
|
|
}
|
|
|
|
uint32_t adi_romtable_entry_count(AppFSM* const ctx, uint32_t base) {
|
|
uint32_t count = 0;
|
|
uint32_t entry = 0;
|
|
|
|
furi_mutex_acquire(ctx->swd_mutex, FuriWaitForever);
|
|
for(size_t pos = 0; pos < 960; pos++) {
|
|
uint8_t ret = 0;
|
|
for(int tries = 0; tries < 10 && ret != 1; tries++) {
|
|
ret = swd_read_memory(ctx, ctx->ap_pos, base + pos * 4, &entry);
|
|
}
|
|
if(ret != 1) {
|
|
DBGS("Read failed");
|
|
break;
|
|
}
|
|
if(!(entry & 1)) {
|
|
break;
|
|
}
|
|
if(entry & 0x00000FFC) {
|
|
break;
|
|
}
|
|
count++;
|
|
}
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
return count;
|
|
}
|
|
|
|
uint32_t adi_romtable_get(AppFSM* const ctx, uint32_t base, uint32_t pos) {
|
|
uint32_t entry = 0;
|
|
|
|
furi_mutex_acquire(ctx->swd_mutex, FuriWaitForever);
|
|
uint8_t ret = swd_read_memory(ctx, ctx->ap_pos, base + pos * 4, &entry);
|
|
if(ret != 1) {
|
|
DBGS("Read failed");
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
return 0;
|
|
}
|
|
furi_mutex_release(ctx->swd_mutex);
|
|
|
|
return base + (entry & 0xFFFFF000);
|
|
}
|
|
|
|
bool adi_is_romtable(AppFSM* const ctx, uint32_t base) {
|
|
uint8_t class = 0;
|
|
|
|
if(!adi_get_class(ctx, base, &class)) {
|
|
return false;
|
|
}
|
|
|
|
if(class != CIDR_CLASS_ROMTABLE) {
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|