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r3df0xx 2022-05-19 01:35:30 +03:00
parent 911404e881
commit c12fc57997
1 changed files with 0 additions and 56 deletions
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56
applications/subghz/helpers/subghz_frequency_analyzer_worker.c
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@ -5,13 +5,9 @@
#include "../subghz_i.h" #include "../subghz_i.h"
<<<<<<< HEAD
#define SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD -90.0f
=======
#define TAG "SubghzFrequencyAnalyzerWorker" #define TAG "SubghzFrequencyAnalyzerWorker"
#define SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD -95.0f #define SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD -95.0f
>>>>>>> upstream/dev
static const uint8_t subghz_preset_ook_58khz[][2] = { static const uint8_t subghz_preset_ook_58khz[][2] = {
{CC1101_MDMCFG4, 0b11110111}, // Rx BW filter is 58.035714kHz {CC1101_MDMCFG4, 0b11110111}, // Rx BW filter is 58.035714kHz
@ -41,11 +37,7 @@ struct SubGhzFrequencyAnalyzerWorker {
static void subghz_frequency_analyzer_worker_load_registers(const uint8_t data[][2]) { static void subghz_frequency_analyzer_worker_load_registers(const uint8_t data[][2]) {
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
<<<<<<< HEAD
uint32_t i = 0;
=======
size_t i = 0; size_t i = 0;
>>>>>>> upstream/dev
while(data[i][0]) { while(data[i][0]) {
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, data[i][0], data[i][1]); cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, data[i][0], data[i][1]);
i++; i++;
@ -78,14 +70,8 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
SubGhzFrequencyAnalyzerWorker* instance = context; SubGhzFrequencyAnalyzerWorker* instance = context;
FrequencyRSSI frequency_rssi = {.frequency = 0, .rssi = 0}; FrequencyRSSI frequency_rssi = {.frequency = 0, .rssi = 0};
<<<<<<< HEAD
float rssi;
uint32_t frequency;
uint32_t frequency_start;
=======
float rssi = 0; float rssi = 0;
uint32_t frequency = 0; uint32_t frequency = 0;
>>>>>>> upstream/dev
CC1101Status status; CC1101Status status;
//Start CC1101 //Start CC1101
@ -95,20 +81,6 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
cc1101_flush_rx(&furi_hal_spi_bus_handle_subghz); cc1101_flush_rx(&furi_hal_spi_bus_handle_subghz);
cc1101_flush_tx(&furi_hal_spi_bus_handle_subghz); cc1101_flush_tx(&furi_hal_spi_bus_handle_subghz);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW); cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW);
<<<<<<< HEAD
cc1101_write_reg(
&furi_hal_spi_bus_handle_subghz,
CC1101_AGCCTRL2,
0b0000111); // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
cc1101_write_reg(
&furi_hal_spi_bus_handle_subghz,
CC1101_AGCCTRL1,
0b00000000); // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
cc1101_write_reg(
&furi_hal_spi_bus_handle_subghz,
CC1101_AGCCTRL0,
0b00000001); // 00 - No hysteresis, medium asymmetric dead zone, medium gain ; 00 - 8 samples agc; 00 - Normal AGC, 01 - 8dB boundary
=======
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_MDMCFG3, cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_MDMCFG3,
0b11111111); // symbol rate 0b11111111); // symbol rate
cc1101_write_reg( cc1101_write_reg(
@ -123,7 +95,6 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
&furi_hal_spi_bus_handle_subghz, &furi_hal_spi_bus_handle_subghz,
CC1101_AGCCTRL0, CC1101_AGCCTRL0,
0b00110000); // 00 - No hysteresis, medium asymmetric dead zone, medium gain ; 11 - 64 samples agc; 00 - Normal AGC, 00 - 4dB boundary 0b00110000); // 00 - No hysteresis, medium asymmetric dead zone, medium gain ; 11 - 64 samples agc; 00 - Normal AGC, 00 - 4dB boundary
>>>>>>> upstream/dev
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
@ -140,10 +111,7 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
furi_hal_subghz_idle(); furi_hal_subghz_idle();
subghz_frequency_analyzer_worker_load_registers(subghz_preset_ook_650khz); subghz_frequency_analyzer_worker_load_registers(subghz_preset_ook_650khz);
<<<<<<< HEAD
=======
// First stage: coarse scan // First stage: coarse scan
>>>>>>> upstream/dev
for(size_t i = 0; i < subghz_setting_get_frequency_count(instance->setting); i++) { for(size_t i = 0; i < subghz_setting_get_frequency_count(instance->setting); i++) {
if(furi_hal_subghz_is_frequency_valid( if(furi_hal_subghz_is_frequency_valid(
subghz_setting_get_frequency(instance->setting, i))) { subghz_setting_get_frequency(instance->setting, i))) {
@ -161,13 +129,9 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
cc1101_switch_to_rx(&furi_hal_spi_bus_handle_subghz); cc1101_switch_to_rx(&furi_hal_spi_bus_handle_subghz);
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
<<<<<<< HEAD
osDelay(3);
=======
// delay will be in range between 1 and 2ms // delay will be in range between 1 and 2ms
osDelay(2); osDelay(2);
>>>>>>> upstream/dev
rssi = furi_hal_subghz_get_rssi(); rssi = furi_hal_subghz_get_rssi();
rssi_avg += rssi; rssi_avg += rssi;
@ -182,16 +146,6 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
} }
} }
<<<<<<< HEAD
if(frequency_rssi.rssi > SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD) {
// -0.5 ... 433.92 ... +0.5
frequency_start = frequency_rssi.frequency - 500000;
frequency_rssi.rssi = -127.0;
furi_hal_subghz_idle();
subghz_frequency_analyzer_worker_load_registers(subghz_preset_ook_58khz);
//step 10KHz
for(uint32_t i = frequency_start; i < frequency_start + 500000; i += 10000) {
=======
FURI_LOG_T( FURI_LOG_T(
TAG, TAG,
"RSSI: avg %f, max %f at %u, min %f", "RSSI: avg %f, max %f at %u, min %f",
@ -211,7 +165,6 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
for(uint32_t i = frequency_rssi.frequency - 300000; for(uint32_t i = frequency_rssi.frequency - 300000;
i < frequency_rssi.frequency + 300000; i < frequency_rssi.frequency + 300000;
i += 20000) { i += 20000) {
>>>>>>> upstream/dev
if(furi_hal_subghz_is_frequency_valid(i)) { if(furi_hal_subghz_is_frequency_valid(i)) {
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
cc1101_switch_to_idle(&furi_hal_spi_bus_handle_subghz); cc1101_switch_to_idle(&furi_hal_spi_bus_handle_subghz);
@ -225,13 +178,9 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
cc1101_switch_to_rx(&furi_hal_spi_bus_handle_subghz); cc1101_switch_to_rx(&furi_hal_spi_bus_handle_subghz);
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
<<<<<<< HEAD
osDelay(5);
=======
// delay will be in range between 1 and 2ms // delay will be in range between 1 and 2ms
osDelay(2); osDelay(2);
>>>>>>> upstream/dev
rssi = furi_hal_subghz_get_rssi(); rssi = furi_hal_subghz_get_rssi();
if(frequency_rssi.rssi < rssi) { if(frequency_rssi.rssi < rssi) {
frequency_rssi.rssi = rssi; frequency_rssi.rssi = rssi;
@ -241,16 +190,11 @@ static int32_t subghz_frequency_analyzer_worker_thread(void* context) {
} }
} }
<<<<<<< HEAD
if(frequency_rssi.rssi > SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD) {
instance->count_repet = 20;
=======
// Deliver results // Deliver results
if(frequency_rssi.rssi > SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD) { if(frequency_rssi.rssi > SUBGHZ_FREQUENCY_ANALYZER_THRESHOLD) {
FURI_LOG_D(TAG, "=:%u:%f", frequency_rssi.frequency, (double)frequency_rssi.rssi); FURI_LOG_D(TAG, "=:%u:%f", frequency_rssi.frequency, (double)frequency_rssi.rssi);
instance->sample_hold_counter = 20; instance->sample_hold_counter = 20;
>>>>>>> upstream/dev
if(instance->filVal) { if(instance->filVal) {
frequency_rssi.frequency = frequency_rssi.frequency =
subghz_frequency_analyzer_worker_expRunningAverageAdaptive( subghz_frequency_analyzer_worker_expRunningAverageAdaptive(