mirror of
https://github.com/DarkFlippers/unleashed-firmware
synced 2024-09-20 22:52:01 +00:00
IRDA: Use DMA for async TX (#608)
This commit is contained in:
Albert Kharisov
GitHub
parent
9c38efd4ef
commit
ba399abb5d
9 changed files with 657 additions and 162 deletions
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@ -10,6 +10,7 @@
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#include <string>
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#include <m-string.h>
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#include <irda_transmit.h>
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#include <sys/types.h>
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static void signal_received_callback(void* context, IrdaWorkerSignal* received_signal) {
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furi_assert(received_signal);
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@ -47,7 +48,7 @@ static void signal_received_callback(void* context, IrdaWorkerSignal* received_s
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}
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static void irda_cli_start_ir_rx(Cli* cli, string_t args, void* context) {
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if(api_hal_irda_rx_irq_is_busy()) {
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if(api_hal_irda_is_busy()) {
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printf("IRDA is busy. Exit.");
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return;
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}
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@ -105,7 +106,7 @@ static bool parse_signal_raw(
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uint32_t* timings,
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uint32_t* timings_cnt,
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float* duty_cycle,
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float* frequency) {
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uint32_t* frequency) {
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char frequency_str[10];
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char duty_cycle_str[10];
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int parsed = sscanf(str, "RAW F:%9s DC:%9s", frequency_str, duty_cycle_str);
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@ -141,14 +142,14 @@ static bool parse_signal_raw(
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}
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static void irda_cli_start_ir_tx(Cli* cli, string_t args, void* context) {
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if(api_hal_irda_rx_irq_is_busy()) {
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if(api_hal_irda_is_busy()) {
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printf("IRDA is busy. Exit.");
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return;
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}
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IrdaMessage message;
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const char* str = string_get_cstr(args);
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float frequency;
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uint32_t frequency;
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float duty_cycle;
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uint32_t* timings = (uint32_t*)furi_alloc(sizeof(uint32_t) * 1000);
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uint32_t timings_cnt = 1000;
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@ -156,7 +157,7 @@ static void irda_cli_start_ir_tx(Cli* cli, string_t args, void* context) {
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if(parse_message(str, &message)) {
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irda_send(&message, 1);
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} else if(parse_signal_raw(str, timings, &timings_cnt, &duty_cycle, &frequency)) {
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irda_send_raw_ext(timings, timings_cnt, true, duty_cycle, frequency);
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irda_send_raw_ext(timings, timings_cnt, true, frequency, duty_cycle);
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} else {
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printf("Wrong arguments.\r\n");
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irda_cli_print_usage();
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@ -1,11 +1,21 @@
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ApiHalIrdaTxGetDataStateError, /* An error occured during transmission */
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ApiHalIrdaTxGetDataStateOk, /* New data obtained */
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ApiHalIrdaTxGetDataStateDone, /* New data obtained, and this is end of package */
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ApiHalIrdaTxGetDataStateLastDone, /* New data obtained, and this is end of package and no more data available */
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} ApiHalIrdaTxGetDataState;
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typedef ApiHalIrdaTxGetDataState (*ApiHalIrdaTxGetDataCallback) (void* context, uint32_t* duration, bool* level);
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/**
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* Signature of callback function for receiving continuous IRDA rx signal.
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*
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@ -13,26 +23,26 @@ extern "C" {
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* @param level[in] - level of input IRDA rx signal
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* @param duration[in] - duration of continuous rx signal level in us
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*/
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typedef void (*ApiHalIrdaCaptureCallback)(void* ctx, bool level, uint32_t duration);
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typedef void (*ApiHalIrdaRxCaptureCallback)(void* ctx, bool level, uint32_t duration);
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/**
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* Signature of callback function for reaching silence timeout on IRDA port.
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*
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* @param ctx[in] - context to pass to callback
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*/
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typedef void (*ApiHalIrdaTimeoutCallback)(void* ctx);
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typedef void (*ApiHalIrdaRxTimeoutCallback)(void* ctx);
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/**
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* Initialize IRDA RX timer to receive interrupts.
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* It provides interrupts for every RX-signal edge changing
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* with its duration.
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*/
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void api_hal_irda_rx_irq_init(void);
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void api_hal_irda_async_rx_start(void);
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/**
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* Deinitialize IRDA RX interrupt.
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*/
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void api_hal_irda_rx_irq_deinit(void);
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void api_hal_irda_async_rx_stop(void);
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/** Setup api hal for receiving silence timeout.
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* Should be used with 'api_hal_irda_timeout_irq_set_callback()'.
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@ -40,7 +50,7 @@ void api_hal_irda_rx_irq_deinit(void);
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* @param[in] timeout_ms - time to wait for silence on IRDA port
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* before generating IRQ.
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*/
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void api_hal_irda_rx_timeout_irq_init(uint32_t timeout_ms);
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void api_hal_irda_async_rx_set_timeout(uint32_t timeout_ms);
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/**
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* Setup callback for previously initialized IRDA RX interrupt.
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@ -48,7 +58,7 @@ void api_hal_irda_rx_timeout_irq_init(uint32_t timeout_ms);
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* @param[in] callback - callback to call when RX signal edge changing occurs
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* @param[in] ctx - context for callback
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*/
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void api_hal_irda_rx_irq_set_callback(ApiHalIrdaCaptureCallback callback, void *ctx);
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void api_hal_irda_async_rx_set_capture_isr_callback(ApiHalIrdaRxCaptureCallback callback, void *ctx);
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/**
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* Setup callback for reaching silence timeout on IRDA port.
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@ -57,27 +67,53 @@ void api_hal_irda_rx_irq_set_callback(ApiHalIrdaCaptureCallback callback, void *
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* @param[in] callback - callback for silence timeout
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* @param[in] ctx - context to pass to callback
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*/
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void api_hal_irda_rx_timeout_irq_set_callback(ApiHalIrdaTimeoutCallback callback, void *ctx);
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/**
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* Start generating IRDA TX PWM. Provides PWM initialization on
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* defined frequency.
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*
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* @param[in] duty_cycle - duty cycle
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* @param[in] freq - PWM frequency to generate
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*/
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void api_hal_irda_pwm_set(float duty_cycle, float freq);
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/**
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* Stop generating IRDA PWM signal.
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*/
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void api_hal_irda_pwm_stop();
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void api_hal_irda_async_rx_set_timeout_isr_callback(ApiHalIrdaRxTimeoutCallback callback, void *ctx);
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/**
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* Check if IRDA is in use now.
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* @return false - IRDA is busy, true otherwise.
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* @return true - IRDA is busy, false otherwise.
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*/
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bool api_hal_irda_rx_irq_is_busy(void);
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bool api_hal_irda_is_busy(void);
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/**
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* Set callback providing new data. This function has to be called
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* before api_hal_irda_async_tx_start().
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*
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* @param[in] callback - function to provide new data
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* @param[in] context - context for callback
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*/
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void api_hal_irda_async_tx_set_data_isr_callback(ApiHalIrdaTxGetDataCallback callback, void* context);
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/**
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* Start IR asynchronous transmission. It can be stopped by 2 reasons:
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* 1) implicit call for api_hal_irda_async_tx_stop()
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* 2) callback can provide ApiHalIrdaTxGetDataStateLastDone response
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* which means no more data available for transmission.
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*
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* Any func (api_hal_irda_async_tx_stop() or
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* api_hal_irda_async_tx_wait_termination()) has to be called to wait
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* end of transmission and free resources.
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*
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* @param[in] freq - frequency for PWM
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* @param[in] duty_cycle - duty cycle for PWM
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* @return true if transmission successfully started, false otherwise.
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* If start failed no need to free resources.
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*/
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bool api_hal_irda_async_tx_start(uint32_t freq, float duty_cycle);
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/**
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* Stop IR asynchronous transmission and free resources.
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* Transmission will stop as soon as transmission reaches end of
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* package (ApiHalIrdaTxGetDataStateDone or ApiHalIrdaTxGetDataStateLastDone).
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*/
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void api_hal_irda_async_tx_stop(void);
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/**
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* Wait for end of IR asynchronous transmission and free resources.
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* Transmission will stop as soon as transmission reaches end of
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* transmission (ApiHalIrdaTxGetDataStateLastDone).
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*/
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void api_hal_irda_async_tx_wait_termination(void);
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#ifdef __cplusplus
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}
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@ -32,11 +32,6 @@ void COMP_IRQHandler(void) {
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HAL_COMP_IRQHandler(&hcomp1);
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}
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void TIM1_UP_TIM16_IRQHandler(void) {
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HAL_TIM_IRQHandler(&htim1);
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HAL_TIM_IRQHandler(&htim16);
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}
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void TIM1_TRG_COM_TIM17_IRQHandler(void) {
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HAL_TIM_IRQHandler(&htim1);
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}
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@ -5,6 +5,7 @@
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#include <stm32wbxx_ll_tim.h>
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volatile ApiHalInterruptISR api_hal_tim_tim2_isr = NULL;
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volatile ApiHalInterruptISR api_hal_tim_tim1_isr = NULL;
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#define API_HAL_INTERRUPT_DMA_COUNT 2
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#define API_HAL_INTERRUPT_DMA_CHANNELS_COUNT 8
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@ -32,6 +33,13 @@ void api_hal_interrupt_set_timer_isr(TIM_TypeDef* timer, ApiHalInterruptISR isr)
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furi_assert(api_hal_tim_tim2_isr != NULL);
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}
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api_hal_tim_tim2_isr = isr;
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} else if (timer == TIM1) {
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if (isr) {
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furi_assert(api_hal_tim_tim1_isr == NULL);
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} else {
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furi_assert(api_hal_tim_tim1_isr != NULL);
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}
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api_hal_tim_tim1_isr = isr;
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} else {
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furi_check(0);
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}
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@ -43,7 +51,7 @@ void api_hal_interrupt_set_dma_channel_isr(DMA_TypeDef* dma, uint32_t channel, A
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furi_check(channel < API_HAL_INTERRUPT_DMA_CHANNELS_COUNT);
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if (dma == DMA1) {
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api_hal_dma_channel_isr[0][channel] = isr;
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} else if (dma == DMA1) {
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} else if (dma == DMA2) {
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api_hal_dma_channel_isr[1][channel] = isr;
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} else {
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furi_check(0);
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@ -73,6 +81,15 @@ void TIM2_IRQHandler(void) {
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}
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}
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/* Timer 1 Update */
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void TIM1_UP_TIM16_IRQHandler(void) {
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if (api_hal_tim_tim1_isr) {
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api_hal_tim_tim1_isr();
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} else {
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HAL_TIM_IRQHandler(&htim1);
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}
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}
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/* DMA 1 */
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void DMA1_Channel1_IRQHandler(void) {
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if (api_hal_dma_channel_isr[0][0]) api_hal_dma_channel_isr[0][0]();
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@ -1,4 +1,8 @@
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#include "api-hal-irda.h"
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#include "api-hal-delay.h"
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#include "furi/check.h"
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#include "stm32wbxx_ll_dma.h"
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#include "sys/_stdint.h"
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#include <cmsis_os2.h>
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#include <api-hal-interrupt.h>
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#include <api-hal-resources.h>
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@ -9,81 +13,115 @@
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#include <stdio.h>
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#include <furi.h>
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#include <math.h>
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#include <main.h>
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#include <api-hal-pwm.h>
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static struct{
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ApiHalIrdaCaptureCallback capture_callback;
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#define IRDA_TIM_TX_DMA_BUFFER_SIZE 200
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#define IRDA_POLARITY_SHIFT 1
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#define IRDA_TX_CCMR_HIGH (TIM_CCMR2_OC3PE | LL_TIM_OCMODE_PWM2) /* Mark time - enable PWM2 mode */
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#define IRDA_TX_CCMR_LOW (TIM_CCMR2_OC3PE | LL_TIM_OCMODE_FORCED_INACTIVE) /* Space time - force low */
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typedef struct{
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ApiHalIrdaRxCaptureCallback capture_callback;
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void *capture_context;
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ApiHalIrdaTimeoutCallback timeout_callback;
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ApiHalIrdaRxTimeoutCallback timeout_callback;
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void *timeout_context;
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} timer_irda;
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} IrdaTimRx;
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typedef enum{
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TimerIRQSourceCCI1,
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TimerIRQSourceCCI2,
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} TimerIRQSource;
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typedef struct{
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uint8_t* polarity;
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uint16_t* data;
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size_t size;
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bool packet_end;
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bool last_packet_end;
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} IrdaTxBuf;
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static void api_hal_irda_handle_timeout(void) {
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/* Timers CNT register starts to counting from 0 to ARR, but it is
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* reseted when Channel 1 catches interrupt. It is not reseted by
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* channel 2, though, so we have to distract it's values (see TimerIRQSourceCCI1 ISR).
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* This can cause false timeout: when time is over, but we started
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* receiving new signal few microseconds ago, because CNT register
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* is reseted once per period, not per sample. */
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if (LL_GPIO_IsInputPinSet(gpio_irda_rx.port, gpio_irda_rx.pin) == 0)
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return;
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typedef struct {
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float cycle_duration;
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ApiHalIrdaTxGetDataCallback data_callback;
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void* data_context;
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IrdaTxBuf buffer[2];
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osSemaphoreId_t stop_semaphore;
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} IrdaTimTx;
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if (timer_irda.timeout_callback)
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timer_irda.timeout_callback(timer_irda.timeout_context);
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}
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typedef enum {
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IrdaStateIdle, /** Api Hal Irda is ready to start RX or TX */
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IrdaStateAsyncRx, /** Async RX started */
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IrdaStateAsyncTx, /** Async TX started, DMA and timer is on */
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IrdaStateAsyncTxStopReq, /** Async TX started, async stop request received */
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IrdaStateAsyncTxStopInProgress, /** Async TX started, stop request is processed and we wait for last data to be sent */
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IrdaStateAsyncTxStopped, /** Async TX complete, cleanup needed */
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IrdaStateMAX,
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} IrdaState;
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/* High pin level is a Space state of IRDA signal. Invert level for further processing. */
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static void api_hal_irda_handle_capture(TimerIRQSource source) {
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uint32_t duration = 0;
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bool level = 0;
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static volatile IrdaState api_hal_irda_state = IrdaStateIdle;
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static IrdaTimTx irda_tim_tx;
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static IrdaTimRx irda_tim_rx;
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switch (source) {
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case TimerIRQSourceCCI1:
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duration = LL_TIM_IC_GetCaptureCH1(TIM2) - LL_TIM_IC_GetCaptureCH2(TIM2);
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level = 1;
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break;
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case TimerIRQSourceCCI2:
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duration = LL_TIM_IC_GetCaptureCH2(TIM2);
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level = 0;
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break;
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default:
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furi_check(0);
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}
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static bool api_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift);
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static void api_hal_irda_async_tx_free_resources(void);
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static void api_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift);
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static void api_hal_irda_tx_dma_set_buffer(uint8_t buf_num);
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static void api_hal_irda_tx_fill_buffer_last(uint8_t buf_num);
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static uint8_t api_hal_irda_get_current_dma_tx_buffer(void);
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static void api_hal_irda_tx_dma_polarity_isr();
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static void api_hal_irda_tx_dma_isr();
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if (timer_irda.capture_callback)
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timer_irda.capture_callback(timer_irda.capture_context, level, duration);
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}
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static void api_hal_irda_tim_rx_isr() {
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static void api_hal_irda_isr() {
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/* Timeout */
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if(LL_TIM_IsActiveFlag_CC3(TIM2)) {
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LL_TIM_ClearFlag_CC3(TIM2);
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api_hal_irda_handle_timeout();
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}
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if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
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LL_TIM_ClearFlag_CC1(TIM2);
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furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
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if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC1S)) {
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// input capture
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api_hal_irda_handle_capture(TimerIRQSourceCCI1);
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/* Timers CNT register starts to counting from 0 to ARR, but it is
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* reseted when Channel 1 catches interrupt. It is not reseted by
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* channel 2, though, so we have to distract it's values (see TimerIRQSourceCCI1 ISR).
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* This can cause false timeout: when time is over, but we started
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* receiving new signal few microseconds ago, because CNT register
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* is reseted once per period, not per sample. */
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if (LL_GPIO_IsInputPinSet(gpio_irda_rx.port, gpio_irda_rx.pin) != 0) {
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if (irda_tim_rx.timeout_callback)
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irda_tim_rx.timeout_callback(irda_tim_rx.timeout_context);
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}
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}
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/* Rising Edge */
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if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
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LL_TIM_ClearFlag_CC1(TIM2);
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furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
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if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC1S)) {
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/* Low pin level is a Mark state of IRDA signal. Invert level for further processing. */
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uint32_t duration = LL_TIM_IC_GetCaptureCH1(TIM2) - LL_TIM_IC_GetCaptureCH2(TIM2);
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if (irda_tim_rx.capture_callback)
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irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 1, duration);
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} else {
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furi_assert(0);
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}
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}
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/* Falling Edge */
|
||||
if(LL_TIM_IsActiveFlag_CC2(TIM2)) {
|
||||
LL_TIM_ClearFlag_CC2(TIM2);
|
||||
furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
|
||||
|
||||
if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC2S)) {
|
||||
// input capture
|
||||
api_hal_irda_handle_capture(TimerIRQSourceCCI2);
|
||||
/* High pin level is a Space state of IRDA signal. Invert level for further processing. */
|
||||
uint32_t duration = LL_TIM_IC_GetCaptureCH2(TIM2);
|
||||
if (irda_tim_rx.capture_callback)
|
||||
irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 0, duration);
|
||||
} else {
|
||||
furi_assert(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void api_hal_irda_rx_irq_init(void) {
|
||||
void api_hal_irda_async_rx_start(void) {
|
||||
furi_assert(api_hal_irda_state == IrdaStateIdle);
|
||||
|
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
||||
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
|
||||
|
||||
|
|
@ -114,50 +152,433 @@ void api_hal_irda_rx_irq_init(void) {
|
|||
LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_INDIRECTTI);
|
||||
LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
|
||||
|
||||
api_hal_interrupt_set_timer_isr(TIM2, api_hal_irda_tim_rx_isr);
|
||||
api_hal_irda_state = IrdaStateAsyncRx;
|
||||
|
||||
LL_TIM_EnableIT_CC1(TIM2);
|
||||
LL_TIM_EnableIT_CC2(TIM2);
|
||||
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
|
||||
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
|
||||
|
||||
api_hal_interrupt_set_timer_isr(TIM2, api_hal_irda_isr);
|
||||
|
||||
LL_TIM_SetCounter(TIM2, 0);
|
||||
LL_TIM_EnableCounter(TIM2);
|
||||
|
||||
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
|
||||
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
||||
NVIC_EnableIRQ(TIM2_IRQn);
|
||||
}
|
||||
|
||||
void api_hal_irda_rx_irq_deinit(void) {
|
||||
void api_hal_irda_async_rx_stop(void) {
|
||||
furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
|
||||
LL_TIM_DeInit(TIM2);
|
||||
api_hal_interrupt_set_timer_isr(TIM2, NULL);
|
||||
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
||||
api_hal_irda_state = IrdaStateIdle;
|
||||
}
|
||||
|
||||
void api_hal_irda_rx_timeout_irq_init(uint32_t timeout_ms) {
|
||||
void api_hal_irda_async_rx_set_timeout(uint32_t timeout_ms) {
|
||||
LL_TIM_OC_SetCompareCH3(TIM2, timeout_ms * 1000);
|
||||
LL_TIM_OC_SetMode(TIM2, LL_TIM_CHANNEL_CH3, LL_TIM_OCMODE_ACTIVE);
|
||||
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH3);
|
||||
LL_TIM_EnableIT_CC3(TIM2);
|
||||
}
|
||||
|
||||
bool api_hal_irda_rx_irq_is_busy(void) {
|
||||
return (LL_TIM_IsEnabledIT_CC1(TIM2) || LL_TIM_IsEnabledIT_CC2(TIM2));
|
||||
bool api_hal_irda_is_busy(void) {
|
||||
return api_hal_irda_state != IrdaStateIdle;
|
||||
}
|
||||
|
||||
void api_hal_irda_rx_irq_set_callback(ApiHalIrdaCaptureCallback callback, void *ctx) {
|
||||
timer_irda.capture_callback = callback;
|
||||
timer_irda.capture_context = ctx;
|
||||
void api_hal_irda_async_rx_set_capture_isr_callback(ApiHalIrdaRxCaptureCallback callback, void *ctx) {
|
||||
irda_tim_rx.capture_callback = callback;
|
||||
irda_tim_rx.capture_context = ctx;
|
||||
}
|
||||
|
||||
void api_hal_irda_rx_timeout_irq_set_callback(ApiHalIrdaTimeoutCallback callback, void *ctx) {
|
||||
timer_irda.timeout_callback = callback;
|
||||
timer_irda.timeout_context = ctx;
|
||||
void api_hal_irda_async_rx_set_timeout_isr_callback(ApiHalIrdaRxTimeoutCallback callback, void *ctx) {
|
||||
irda_tim_rx.timeout_callback = callback;
|
||||
irda_tim_rx.timeout_context = ctx;
|
||||
}
|
||||
|
||||
void api_hal_irda_pwm_set(float value, float freq) {
|
||||
hal_pwmn_set(value, freq, &IRDA_TX_TIM, IRDA_TX_CH);
|
||||
static void api_hal_irda_tx_dma_terminate(void) {
|
||||
LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_1);
|
||||
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
|
||||
LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_2);
|
||||
|
||||
furi_assert(api_hal_irda_state == IrdaStateAsyncTxStopInProgress);
|
||||
|
||||
LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_1);
|
||||
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
|
||||
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
|
||||
LL_TIM_DisableCounter(TIM1);
|
||||
osStatus_t status = osSemaphoreRelease(irda_tim_tx.stop_semaphore);
|
||||
furi_check(status == osOK);
|
||||
api_hal_irda_state = IrdaStateAsyncTxStopped;
|
||||
}
|
||||
|
||||
void api_hal_irda_pwm_stop() {
|
||||
hal_pwmn_stop(&IRDA_TX_TIM, IRDA_TX_CH);
|
||||
static uint8_t api_hal_irda_get_current_dma_tx_buffer(void) {
|
||||
uint8_t buf_num = 0;
|
||||
uint32_t buffer_adr = LL_DMA_GetMemoryAddress(DMA1, LL_DMA_CHANNEL_2);
|
||||
if (buffer_adr == (uint32_t) irda_tim_tx.buffer[0].data) {
|
||||
buf_num = 0;
|
||||
} else if (buffer_adr == (uint32_t) irda_tim_tx.buffer[1].data) {
|
||||
buf_num = 1;
|
||||
} else {
|
||||
furi_assert(0);
|
||||
}
|
||||
return buf_num;
|
||||
}
|
||||
|
||||
static void api_hal_irda_tx_dma_polarity_isr() {
|
||||
if (LL_DMA_IsActiveFlag_TE1(DMA1)) {
|
||||
LL_DMA_ClearFlag_TE1(DMA1);
|
||||
furi_check(0);
|
||||
}
|
||||
if (LL_DMA_IsActiveFlag_TC1(DMA1) && LL_DMA_IsEnabledIT_TC(DMA1, LL_DMA_CHANNEL_1)) {
|
||||
LL_DMA_ClearFlag_TC1(DMA1);
|
||||
|
||||
furi_check((api_hal_irda_state == IrdaStateAsyncTx)
|
||||
|| (api_hal_irda_state == IrdaStateAsyncTxStopReq)
|
||||
|| (api_hal_irda_state == IrdaStateAsyncTxStopInProgress));
|
||||
/* actually TC2 is processed and buffer is next buffer */
|
||||
uint8_t next_buf_num = api_hal_irda_get_current_dma_tx_buffer();
|
||||
api_hal_irda_tx_dma_set_polarity(next_buf_num, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void api_hal_irda_tx_dma_isr() {
|
||||
if (LL_DMA_IsActiveFlag_TE2(DMA1)) {
|
||||
LL_DMA_ClearFlag_TE2(DMA1);
|
||||
furi_check(0);
|
||||
}
|
||||
if (LL_DMA_IsActiveFlag_HT2(DMA1) && LL_DMA_IsEnabledIT_HT(DMA1, LL_DMA_CHANNEL_2)) {
|
||||
LL_DMA_ClearFlag_HT2(DMA1);
|
||||
uint8_t buf_num = api_hal_irda_get_current_dma_tx_buffer();
|
||||
uint8_t next_buf_num = !buf_num;
|
||||
if (irda_tim_tx.buffer[buf_num].last_packet_end) {
|
||||
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
|
||||
} else if (!irda_tim_tx.buffer[buf_num].packet_end || (api_hal_irda_state == IrdaStateAsyncTx)) {
|
||||
bool result = api_hal_irda_tx_fill_buffer(next_buf_num, 0);
|
||||
if (irda_tim_tx.buffer[next_buf_num].last_packet_end) {
|
||||
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
|
||||
}
|
||||
if (!result) {
|
||||
furi_assert(0);
|
||||
api_hal_irda_state = IrdaStateAsyncTxStopReq;
|
||||
}
|
||||
} else if (api_hal_irda_state == IrdaStateAsyncTxStopReq) {
|
||||
/* fallthrough */
|
||||
} else {
|
||||
furi_check(0);
|
||||
}
|
||||
}
|
||||
if (LL_DMA_IsActiveFlag_TC2(DMA1) && LL_DMA_IsEnabledIT_TC(DMA1, LL_DMA_CHANNEL_2)) {
|
||||
LL_DMA_ClearFlag_TC2(DMA1);
|
||||
furi_check((api_hal_irda_state == IrdaStateAsyncTxStopInProgress)
|
||||
|| (api_hal_irda_state == IrdaStateAsyncTxStopReq)
|
||||
|| (api_hal_irda_state == IrdaStateAsyncTx));
|
||||
|
||||
uint8_t buf_num = api_hal_irda_get_current_dma_tx_buffer();
|
||||
uint8_t next_buf_num = !buf_num;
|
||||
if (api_hal_irda_state == IrdaStateAsyncTxStopInProgress) {
|
||||
api_hal_irda_tx_dma_terminate();
|
||||
} else if (irda_tim_tx.buffer[buf_num].last_packet_end
|
||||
|| (irda_tim_tx.buffer[buf_num].packet_end && (api_hal_irda_state == IrdaStateAsyncTxStopReq))) {
|
||||
api_hal_irda_state = IrdaStateAsyncTxStopInProgress;
|
||||
api_hal_irda_tx_fill_buffer_last(next_buf_num);
|
||||
api_hal_irda_tx_dma_set_buffer(next_buf_num);
|
||||
} else {
|
||||
/* if it's not end of the packet - continue receiving */
|
||||
api_hal_irda_tx_dma_set_buffer(next_buf_num);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void api_hal_irda_configure_tim_pwm_tx(uint32_t freq, float duty_cycle)
|
||||
{
|
||||
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
|
||||
/* LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP); */
|
||||
|
||||
LL_TIM_DisableCounter(TIM1);
|
||||
LL_TIM_SetRepetitionCounter(TIM1, 0);
|
||||
LL_TIM_SetCounter(TIM1, 0);
|
||||
LL_TIM_SetPrescaler(TIM1, 0);
|
||||
LL_TIM_SetCounterMode(TIM1, LL_TIM_COUNTERMODE_UP);
|
||||
LL_TIM_EnableARRPreload(TIM1);
|
||||
LL_TIM_SetAutoReload(TIM1, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIM1), freq));
|
||||
LL_TIM_OC_SetCompareCH3(TIM1, ( (LL_TIM_GetAutoReload(TIM1) + 1 ) * (1 - duty_cycle)));
|
||||
LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH3);
|
||||
/* LL_TIM_OCMODE_PWM2 set by DMA */
|
||||
LL_TIM_OC_SetMode(TIM1, LL_TIM_CHANNEL_CH3, LL_TIM_OCMODE_FORCED_INACTIVE);
|
||||
LL_TIM_OC_SetPolarity(TIM1, LL_TIM_CHANNEL_CH3N, LL_TIM_OCPOLARITY_HIGH);
|
||||
LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH3);
|
||||
LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH3N);
|
||||
LL_TIM_DisableIT_CC3(TIM1);
|
||||
LL_TIM_DisableMasterSlaveMode(TIM1);
|
||||
LL_TIM_EnableAllOutputs(TIM1);
|
||||
LL_TIM_DisableIT_UPDATE(TIM1);
|
||||
LL_TIM_EnableDMAReq_UPDATE(TIM1);
|
||||
|
||||
NVIC_SetPriority(TIM1_UP_TIM16_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
||||
NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
|
||||
}
|
||||
|
||||
static void api_hal_irda_configure_tim_cmgr2_dma_tx(void) {
|
||||
LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
|
||||
|
||||
LL_DMA_InitTypeDef dma_config = {0};
|
||||
dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->CCMR2);
|
||||
dma_config.MemoryOrM2MDstAddress = (uint32_t) NULL;
|
||||
dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
|
||||
dma_config.Mode = LL_DMA_MODE_NORMAL;
|
||||
dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
|
||||
dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
|
||||
/* fill word to have other bits set to 0 */
|
||||
dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
|
||||
dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
|
||||
dma_config.NbData = 0;
|
||||
dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM1_UP;
|
||||
dma_config.Priority = LL_DMA_PRIORITY_VERYHIGH;
|
||||
LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
|
||||
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, api_hal_irda_tx_dma_polarity_isr);
|
||||
LL_DMA_ClearFlag_TE1(DMA1);
|
||||
LL_DMA_ClearFlag_TC1(DMA1);
|
||||
LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_1);
|
||||
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
|
||||
|
||||
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
|
||||
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
|
||||
}
|
||||
|
||||
static void api_hal_irda_configure_tim_rcr_dma_tx(void) {
|
||||
LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
|
||||
|
||||
LL_DMA_InitTypeDef dma_config = {0};
|
||||
dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->RCR);
|
||||
dma_config.MemoryOrM2MDstAddress = (uint32_t) NULL;
|
||||
dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
|
||||
dma_config.Mode = LL_DMA_MODE_NORMAL;
|
||||
dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
|
||||
dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
|
||||
dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
|
||||
dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
|
||||
dma_config.NbData = 0;
|
||||
dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM1_UP;
|
||||
dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
|
||||
LL_DMA_Init(DMA1, LL_DMA_CHANNEL_2, &dma_config);
|
||||
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_2, api_hal_irda_tx_dma_isr);
|
||||
LL_DMA_ClearFlag_TC2(DMA1);
|
||||
LL_DMA_ClearFlag_HT2(DMA1);
|
||||
LL_DMA_ClearFlag_TE2(DMA1);
|
||||
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_2);
|
||||
LL_DMA_EnableIT_HT(DMA1, LL_DMA_CHANNEL_2);
|
||||
LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_2);
|
||||
|
||||
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
|
||||
NVIC_EnableIRQ(DMA1_Channel2_IRQn);
|
||||
}
|
||||
|
||||
static void api_hal_irda_tx_fill_buffer_last(uint8_t buf_num) {
|
||||
furi_assert(buf_num < 2);
|
||||
furi_assert(api_hal_irda_state != IrdaStateAsyncRx);
|
||||
furi_assert(api_hal_irda_state < IrdaStateMAX);
|
||||
furi_assert(irda_tim_tx.data_callback);
|
||||
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
|
||||
furi_assert(buffer->data != NULL);
|
||||
furi_assert(buffer->polarity != NULL);
|
||||
|
||||
irda_tim_tx.buffer[buf_num].data[0] = 0; // 1 pulse
|
||||
irda_tim_tx.buffer[buf_num].polarity[0] = IRDA_TX_CCMR_LOW;
|
||||
irda_tim_tx.buffer[buf_num].data[1] = 0; // 1 pulse
|
||||
irda_tim_tx.buffer[buf_num].polarity[1] = IRDA_TX_CCMR_LOW;
|
||||
irda_tim_tx.buffer[buf_num].size = 2;
|
||||
irda_tim_tx.buffer[buf_num].last_packet_end = true;
|
||||
irda_tim_tx.buffer[buf_num].packet_end = true;
|
||||
}
|
||||
|
||||
static bool api_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift) {
|
||||
furi_assert(buf_num < 2);
|
||||
furi_assert(api_hal_irda_state != IrdaStateAsyncRx);
|
||||
furi_assert(api_hal_irda_state < IrdaStateMAX);
|
||||
furi_assert(irda_tim_tx.data_callback);
|
||||
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
|
||||
furi_assert(buffer->data != NULL);
|
||||
furi_assert(buffer->polarity != NULL);
|
||||
|
||||
ApiHalIrdaTxGetDataState status = ApiHalIrdaTxGetDataStateOk;
|
||||
uint32_t duration = 0;
|
||||
bool level = 0;
|
||||
size_t *size = &buffer->size;
|
||||
size_t polarity_counter = 0;
|
||||
while (polarity_shift--) {
|
||||
buffer->polarity[polarity_counter++] = IRDA_TX_CCMR_LOW;
|
||||
}
|
||||
|
||||
for (*size = 0; (*size < IRDA_TIM_TX_DMA_BUFFER_SIZE) && (status == ApiHalIrdaTxGetDataStateOk); ++(*size), ++polarity_counter) {
|
||||
status = irda_tim_tx.data_callback(irda_tim_tx.data_context, &duration, &level);
|
||||
if (status == ApiHalIrdaTxGetDataStateError) {
|
||||
furi_assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t num_of_impulses = roundf(duration / irda_tim_tx.cycle_duration);
|
||||
|
||||
if ((buffer->data[*size] + num_of_impulses - 1) > 0xFFFF) {
|
||||
furi_assert(0);
|
||||
status = ApiHalIrdaTxGetDataStateError;
|
||||
break;
|
||||
}
|
||||
|
||||
buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
|
||||
buffer->data[*size] = num_of_impulses - 1;
|
||||
}
|
||||
|
||||
buffer->last_packet_end = (status == ApiHalIrdaTxGetDataStateLastDone);
|
||||
buffer->packet_end = buffer->last_packet_end || (status == ApiHalIrdaTxGetDataStateDone);
|
||||
|
||||
return status != ApiHalIrdaTxGetDataStateError;
|
||||
}
|
||||
|
||||
static void api_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift) {
|
||||
furi_assert(buf_num < 2);
|
||||
furi_assert(api_hal_irda_state < IrdaStateMAX);
|
||||
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
|
||||
furi_assert(buffer->polarity != NULL);
|
||||
|
||||
__disable_irq();
|
||||
bool channel_enabled = LL_DMA_IsEnabledChannel(DMA1, LL_DMA_CHANNEL_1);
|
||||
if (channel_enabled) {
|
||||
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
|
||||
}
|
||||
LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_1, (uint32_t) buffer->polarity);
|
||||
LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, buffer->size + polarity_shift);
|
||||
if (channel_enabled) {
|
||||
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
|
||||
}
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
static void api_hal_irda_tx_dma_set_buffer(uint8_t buf_num) {
|
||||
furi_assert(buf_num < 2);
|
||||
furi_assert(api_hal_irda_state < IrdaStateMAX);
|
||||
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
|
||||
furi_assert(buffer->data != NULL);
|
||||
|
||||
/* non-circular mode requires disabled channel before setup */
|
||||
__disable_irq();
|
||||
bool channel_enabled = LL_DMA_IsEnabledChannel(DMA1, LL_DMA_CHANNEL_2);
|
||||
if (channel_enabled) {
|
||||
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
|
||||
}
|
||||
LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_2, (uint32_t)buffer->data);
|
||||
LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_2, buffer->size);
|
||||
if (channel_enabled) {
|
||||
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
|
||||
}
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
static void api_hal_irda_async_tx_free_resources(void) {
|
||||
furi_assert((api_hal_irda_state == IrdaStateIdle) || (api_hal_irda_state == IrdaStateAsyncTxStopped));
|
||||
osStatus_t status;
|
||||
|
||||
hal_gpio_init_ex(&gpio_irda_tx, GpioModeOutputOpenDrain, GpioPullDown, GpioSpeedLow, 0);
|
||||
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, NULL);
|
||||
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_2, NULL);
|
||||
LL_TIM_DeInit(TIM1);
|
||||
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1);
|
||||
LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
|
||||
|
||||
status = osSemaphoreDelete(irda_tim_tx.stop_semaphore);
|
||||
furi_check(status == osOK);
|
||||
free(irda_tim_tx.buffer[0].data);
|
||||
free(irda_tim_tx.buffer[1].data);
|
||||
free(irda_tim_tx.buffer[0].polarity);
|
||||
free(irda_tim_tx.buffer[1].polarity);
|
||||
|
||||
irda_tim_tx.buffer[0].data = NULL;
|
||||
irda_tim_tx.buffer[1].data = NULL;
|
||||
irda_tim_tx.buffer[0].polarity = NULL;
|
||||
irda_tim_tx.buffer[1].polarity = NULL;
|
||||
}
|
||||
|
||||
bool api_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
|
||||
if ((duty_cycle > 1) || (duty_cycle < 0) || (freq > 40000) || (freq < 10000) || (irda_tim_tx.data_callback == NULL)) {
|
||||
furi_assert(0);
|
||||
return false;
|
||||
}
|
||||
|
||||
furi_assert(api_hal_irda_state == IrdaStateIdle);
|
||||
furi_assert(irda_tim_tx.buffer[0].data == NULL);
|
||||
furi_assert(irda_tim_tx.buffer[1].data == NULL);
|
||||
furi_assert(irda_tim_tx.buffer[0].polarity == NULL);
|
||||
furi_assert(irda_tim_tx.buffer[1].polarity == NULL);
|
||||
|
||||
size_t alloc_size_data = IRDA_TIM_TX_DMA_BUFFER_SIZE * sizeof(uint16_t);
|
||||
irda_tim_tx.buffer[0].data = furi_alloc(alloc_size_data);
|
||||
irda_tim_tx.buffer[1].data = furi_alloc(alloc_size_data);
|
||||
|
||||
size_t alloc_size_polarity = (IRDA_TIM_TX_DMA_BUFFER_SIZE + IRDA_POLARITY_SHIFT) * sizeof(uint8_t);
|
||||
irda_tim_tx.buffer[0].polarity = furi_alloc(alloc_size_polarity);
|
||||
irda_tim_tx.buffer[1].polarity = furi_alloc(alloc_size_polarity);
|
||||
|
||||
irda_tim_tx.stop_semaphore = osSemaphoreNew(1, 0, NULL);
|
||||
irda_tim_tx.cycle_duration = 1000000.0 / freq;
|
||||
|
||||
bool result = api_hal_irda_tx_fill_buffer(0, IRDA_POLARITY_SHIFT);
|
||||
|
||||
if (result) {
|
||||
api_hal_irda_configure_tim_pwm_tx(freq, duty_cycle);
|
||||
api_hal_irda_configure_tim_cmgr2_dma_tx();
|
||||
api_hal_irda_configure_tim_rcr_dma_tx();
|
||||
api_hal_irda_tx_dma_set_polarity(0, IRDA_POLARITY_SHIFT);
|
||||
api_hal_irda_tx_dma_set_buffer(0);
|
||||
|
||||
api_hal_irda_state = IrdaStateAsyncTx;
|
||||
|
||||
LL_TIM_ClearFlag_UPDATE(TIM1);
|
||||
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
|
||||
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
|
||||
delay_us(5);
|
||||
LL_TIM_GenerateEvent_UPDATE(TIM1); /* DMA -> TIMx_RCR */
|
||||
delay_us(5);
|
||||
LL_GPIO_ResetOutputPin(gpio_irda_tx.port, gpio_irda_tx.pin); /* when disable it prevents false pulse */
|
||||
hal_gpio_init_ex(&gpio_irda_tx, GpioModeAltFunctionPushPull, GpioPullUp, GpioSpeedHigh, GpioAltFn1TIM1);
|
||||
|
||||
__disable_irq();
|
||||
LL_TIM_GenerateEvent_UPDATE(TIM1); /* TIMx_RCR -> Repetition counter */
|
||||
LL_TIM_EnableCounter(TIM1);
|
||||
__enable_irq();
|
||||
|
||||
} else {
|
||||
api_hal_irda_async_tx_free_resources();
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
void api_hal_irda_async_tx_wait_termination(void) {
|
||||
furi_assert(api_hal_irda_state >= IrdaStateAsyncTx);
|
||||
furi_assert(api_hal_irda_state < IrdaStateMAX);
|
||||
|
||||
osStatus_t status;
|
||||
status = osSemaphoreAcquire(irda_tim_tx.stop_semaphore, osWaitForever);
|
||||
furi_check(status == osOK);
|
||||
api_hal_irda_async_tx_free_resources();
|
||||
api_hal_irda_state = IrdaStateIdle;
|
||||
}
|
||||
|
||||
void api_hal_irda_async_tx_stop(void) {
|
||||
furi_assert(api_hal_irda_state >= IrdaStateAsyncTx);
|
||||
furi_assert(api_hal_irda_state < IrdaStateMAX);
|
||||
|
||||
__disable_irq();
|
||||
if (api_hal_irda_state == IrdaStateAsyncTx)
|
||||
api_hal_irda_state = IrdaStateAsyncTxStopReq;
|
||||
__enable_irq();
|
||||
|
||||
api_hal_irda_async_tx_wait_termination();
|
||||
}
|
||||
|
||||
void api_hal_irda_async_tx_set_data_isr_callback(ApiHalIrdaTxGetDataCallback callback, void* context) {
|
||||
furi_assert(api_hal_irda_state == IrdaStateIdle);
|
||||
irda_tim_tx.data_callback = callback;
|
||||
irda_tim_tx.data_context = context;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ IrdaDecoderHandler* irda_alloc_decoder(void);
|
|||
/**
|
||||
* Provide to decoder next timing.
|
||||
*
|
||||
* \param[in] handler - handler to IRDA decoders. Should be aquired with \c irda_alloc_decoder().
|
||||
* \param[in] handler - handler to IRDA decoders. Should be acquired with \c irda_alloc_decoder().
|
||||
* \param[in] level - high(true) or low(false) level of input signal to analyze.
|
||||
* it should alternate every call, otherwise it is an error case,
|
||||
* and decoder resets its state and start decoding from the start.
|
||||
|
|
@ -58,14 +58,14 @@ const IrdaMessage* irda_decode(IrdaDecoderHandler* handler, bool level, uint32_t
|
|||
/**
|
||||
* Deinitialize decoder and free allocated memory.
|
||||
*
|
||||
* \param[in] handler - handler to IRDA decoders. Should be aquired with \c irda_alloc_decoder().
|
||||
* \param[in] handler - handler to IRDA decoders. Should be acquired with \c irda_alloc_decoder().
|
||||
*/
|
||||
void irda_free_decoder(IrdaDecoderHandler* handler);
|
||||
|
||||
/**
|
||||
* Reset IRDA decoder.
|
||||
*
|
||||
* \param[in] handler - handler to IRDA decoders. Should be aquired with \c irda_alloc_decoder().
|
||||
* \param[in] handler - handler to IRDA decoders. Should be acquired with \c irda_alloc_decoder().
|
||||
*/
|
||||
void irda_reset_decoder(IrdaDecoderHandler* handler);
|
||||
|
||||
|
|
@ -119,7 +119,7 @@ IrdaEncoderHandler* irda_alloc_encoder(void);
|
|||
/**
|
||||
* Free encoder handler previously allocated with \c irda_alloc_encoder().
|
||||
*
|
||||
* \param[in] handler - handler to IRDA encoder. Should be aquired with \c irda_alloc_encoder().
|
||||
* \param[in] handler - handler to IRDA encoder. Should be acquired with \c irda_alloc_encoder().
|
||||
*/
|
||||
void irda_free_encoder(IrdaEncoderHandler* handler);
|
||||
|
||||
|
|
@ -132,7 +132,7 @@ void irda_free_encoder(IrdaEncoderHandler* handler);
|
|||
* 4) when \c irda_encode() returns IrdaStatusDone, it means new message is fully encoded.
|
||||
* 5) to encode additional timings, just continue calling \c irda_encode().
|
||||
*
|
||||
* \param[in] handler - handler to IRDA encoder. Should be aquired with \c irda_alloc_encoder().
|
||||
* \param[in] handler - handler to IRDA encoder. Should be acquired with \c irda_alloc_encoder().
|
||||
* \param[out] duration - encoded timing.
|
||||
* \param[out] level - encoded level.
|
||||
*
|
||||
|
|
@ -145,7 +145,7 @@ IrdaStatus irda_encode(IrdaEncoderHandler* handler, uint32_t* duration, bool* le
|
|||
* IrdaStatusDone in \c irda_encode(), encoder will encode repeat messages
|
||||
* till the end of time.
|
||||
*
|
||||
* \param[in] handler - handler to IRDA encoder. Should be aquired with \c irda_alloc_encoder().
|
||||
* \param[in] handler - handler to IRDA encoder. Should be acquired with \c irda_alloc_encoder().
|
||||
* \param[in] message - message to encode.
|
||||
*/
|
||||
void irda_reset_encoder(IrdaEncoderHandler* handler, const IrdaMessage* message);
|
||||
|
|
|
|||
|
|
@ -6,72 +6,96 @@
|
|||
#include <api-hal-irda.h>
|
||||
#include <api-hal-delay.h>
|
||||
|
||||
#define IRDA_SET_TX_COMMON(d, l) irda_set_tx((d), (l), IRDA_COMMON_DUTY_CYCLE, IRDA_COMMON_CARRIER_FREQUENCY)
|
||||
static uint32_t irda_tx_number_of_transmissions = 0;
|
||||
static uint32_t irda_tx_raw_timings_index = 0;
|
||||
static uint32_t irda_tx_raw_timings_number = 0;
|
||||
static uint32_t irda_tx_raw_start_from_mark = 0;
|
||||
static bool irda_tx_raw_add_silence = false;
|
||||
|
||||
static void irda_set_tx(uint32_t duration, bool level, float duty_cycle, float frequency) {
|
||||
if (level) {
|
||||
api_hal_irda_pwm_set(duty_cycle, frequency);
|
||||
delay_us(duration);
|
||||
ApiHalIrdaTxGetDataState irda_get_raw_data_callback (void* context, uint32_t* duration, bool* level) {
|
||||
furi_assert(duration);
|
||||
furi_assert(level);
|
||||
furi_assert(context);
|
||||
|
||||
ApiHalIrdaTxGetDataState state = ApiHalIrdaTxGetDataStateOk;
|
||||
const uint32_t* timings = context;
|
||||
|
||||
if (irda_tx_raw_add_silence && (irda_tx_raw_timings_index == 0)) {
|
||||
irda_tx_raw_add_silence = false;
|
||||
*level = false;
|
||||
*duration = 180000; // 180 ms delay between raw packets
|
||||
} else {
|
||||
api_hal_irda_pwm_stop();
|
||||
delay_us(duration);
|
||||
*level = irda_tx_raw_start_from_mark ^ (irda_tx_raw_timings_index % 2);
|
||||
*duration = timings[irda_tx_raw_timings_index++];
|
||||
}
|
||||
|
||||
if (irda_tx_raw_timings_number == irda_tx_raw_timings_index) {
|
||||
state = ApiHalIrdaTxGetDataStateLastDone;
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
void irda_send_raw_ext(const uint32_t timings[], uint32_t timings_cnt, bool start_from_mark, float duty_cycle, float frequency) {
|
||||
__disable_irq();
|
||||
for (uint32_t i = 0; i < timings_cnt; ++i) {
|
||||
irda_set_tx(timings[i], (i % 2) ^ start_from_mark, duty_cycle, frequency);
|
||||
}
|
||||
IRDA_SET_TX_COMMON(0, false);
|
||||
__enable_irq();
|
||||
void irda_send_raw_ext(const uint32_t timings[], uint32_t timings_cnt, bool start_from_mark, uint32_t frequency, float duty_cycle) {
|
||||
furi_assert(timings);
|
||||
furi_assert(timings_cnt > 1);
|
||||
|
||||
irda_tx_raw_start_from_mark = start_from_mark;
|
||||
irda_tx_raw_timings_index = 0;
|
||||
irda_tx_raw_timings_number = timings_cnt;
|
||||
irda_tx_raw_add_silence = start_from_mark;
|
||||
api_hal_irda_async_tx_set_data_isr_callback(irda_get_raw_data_callback, (void*) timings);
|
||||
api_hal_irda_async_tx_start(frequency, duty_cycle);
|
||||
api_hal_irda_async_tx_wait_termination();
|
||||
|
||||
furi_assert(!api_hal_irda_is_busy());
|
||||
}
|
||||
|
||||
void irda_send_raw(const uint32_t timings[], uint32_t timings_cnt, bool start_from_mark) {
|
||||
__disable_irq();
|
||||
for (uint32_t i = 0; i < timings_cnt; ++i) {
|
||||
IRDA_SET_TX_COMMON(timings[i], (i % 2) ^ start_from_mark);
|
||||
irda_send_raw_ext(timings, timings_cnt, start_from_mark, IRDA_COMMON_CARRIER_FREQUENCY, IRDA_COMMON_DUTY_CYCLE);
|
||||
}
|
||||
|
||||
ApiHalIrdaTxGetDataState irda_get_data_callback (void* context, uint32_t* duration, bool* level) {
|
||||
ApiHalIrdaTxGetDataState state = ApiHalIrdaTxGetDataStateError;
|
||||
IrdaEncoderHandler* handler = context;
|
||||
IrdaStatus status = IrdaStatusError;
|
||||
|
||||
if (irda_tx_number_of_transmissions > 0) {
|
||||
status = irda_encode(handler, duration, level);
|
||||
}
|
||||
IRDA_SET_TX_COMMON(0, false);
|
||||
__enable_irq();
|
||||
|
||||
if (status == IrdaStatusError) {
|
||||
state = ApiHalIrdaTxGetDataStateError;
|
||||
} else if (status == IrdaStatusOk) {
|
||||
state = ApiHalIrdaTxGetDataStateOk;
|
||||
} else if (status == IrdaStatusDone) {
|
||||
state = ApiHalIrdaTxGetDataStateDone;
|
||||
if (--irda_tx_number_of_transmissions == 0) {
|
||||
state = ApiHalIrdaTxGetDataStateLastDone;
|
||||
}
|
||||
} else {
|
||||
furi_assert(0);
|
||||
state = ApiHalIrdaTxGetDataStateError;
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
void irda_send(const IrdaMessage* message, int times) {
|
||||
furi_assert(message);
|
||||
furi_assert(times);
|
||||
furi_assert(irda_is_protocol_valid(message->protocol));
|
||||
|
||||
IrdaStatus status;
|
||||
uint32_t duration = 0;
|
||||
bool level = false;
|
||||
IrdaEncoderHandler* handler = irda_alloc_encoder();
|
||||
irda_reset_encoder(handler, message);
|
||||
irda_tx_number_of_transmissions = times;
|
||||
|
||||
/* Hotfix: first timings is space timing, so make delay instead of locking
|
||||
* whole system for that long. Replace when async timing lib will be ready.
|
||||
* This timing doesn't have to be precise.
|
||||
*/
|
||||
status = irda_encode(handler, &duration, &level);
|
||||
furi_assert(status != IrdaStatusError);
|
||||
furi_assert(level == false);
|
||||
delay_us(duration);
|
||||
|
||||
__disable_irq();
|
||||
|
||||
while (times) {
|
||||
status = irda_encode(handler, &duration, &level);
|
||||
if (status != IrdaStatusError) {
|
||||
IRDA_SET_TX_COMMON(duration, level);
|
||||
} else {
|
||||
furi_assert(0);
|
||||
break;
|
||||
}
|
||||
if (status == IrdaStatusDone)
|
||||
--times;
|
||||
}
|
||||
|
||||
IRDA_SET_TX_COMMON(0, false);
|
||||
__enable_irq();
|
||||
api_hal_irda_async_tx_set_data_isr_callback(irda_get_data_callback, handler);
|
||||
api_hal_irda_async_tx_start(IRDA_COMMON_CARRIER_FREQUENCY, IRDA_COMMON_DUTY_CYCLE);
|
||||
api_hal_irda_async_tx_wait_termination();
|
||||
|
||||
irda_free_encoder(handler);
|
||||
|
||||
furi_assert(!api_hal_irda_is_busy());
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#include <api-hal-irda.h>
|
||||
#include <irda.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -33,7 +34,7 @@ void irda_send_raw(const uint32_t timings[], uint32_t timings_cnt, bool start_fr
|
|||
* \param[in] duty_cycle - duty cycle to generate on PWM
|
||||
* \param[in] frequency - frequency to generate on PWM
|
||||
*/
|
||||
void irda_send_raw_ext(const uint32_t timings[], uint32_t timings_cnt, bool start_from_mark, float duty_cycle, float frequency);
|
||||
void irda_send_raw_ext(const uint32_t timings[], uint32_t timings_cnt, bool start_from_mark, uint32_t frequency, float duty_cycle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -190,19 +190,19 @@ void irda_worker_start(IrdaWorker* instance) {
|
|||
furi_thread_start(instance->thread);
|
||||
|
||||
instance->worker_handle = furi_thread_get_thread_id(instance->thread);
|
||||
api_hal_irda_rx_irq_init();
|
||||
api_hal_irda_rx_timeout_irq_init(IRDA_WORKER_RX_TIMEOUT);
|
||||
api_hal_irda_rx_irq_set_callback(irda_worker_rx_callback, instance);
|
||||
api_hal_irda_rx_timeout_irq_set_callback(irda_worker_rx_timeout_callback, instance);
|
||||
api_hal_irda_async_rx_start();
|
||||
api_hal_irda_async_rx_set_timeout(IRDA_WORKER_RX_TIMEOUT);
|
||||
api_hal_irda_async_rx_set_capture_isr_callback(irda_worker_rx_callback, instance);
|
||||
api_hal_irda_async_rx_set_timeout_isr_callback(irda_worker_rx_timeout_callback, instance);
|
||||
}
|
||||
|
||||
void irda_worker_stop(IrdaWorker* instance) {
|
||||
furi_assert(instance);
|
||||
furi_assert(instance->worker_handle);
|
||||
|
||||
api_hal_irda_rx_timeout_irq_set_callback(NULL, NULL);
|
||||
api_hal_irda_rx_irq_set_callback(NULL, NULL);
|
||||
api_hal_irda_rx_irq_deinit();
|
||||
api_hal_irda_async_rx_set_timeout_isr_callback(NULL, NULL);
|
||||
api_hal_irda_async_rx_set_capture_isr_callback(NULL, NULL);
|
||||
api_hal_irda_async_rx_stop();
|
||||
|
||||
xTaskNotify(instance->worker_handle, IRDA_WORKER_EXIT, eSetBits);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue