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https://github.com/AsahiLinux/u-boot
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ffd06e0231
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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74xx_7xx | ||
mpc5xx | ||
mpc5xxx | ||
mpc8xx | ||
mpc8xxx | ||
mpc83xx | ||
mpc85xx | ||
mpc86xx | ||
mpc512x | ||
mpc824x | ||
mpc8220 | ||
mpc8260 | ||
ppc4xx |