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ff94c15a3c
The previous version of am335x-fb.c contained the functionalities of two drivers that this patch has split. It was a video type driver that used the same registration compatible string that now registers a panel type driver. The proof of this is that two compatible strings were referred to within the same driver. There are now two drivers, each with its own compatible string, functions and API. Furthermore, the panel driver, in addition to decoding the display timings, is now also able to manage the backlight. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
106 lines
3 KiB
C
106 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*/
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#ifndef AM335X_FB_H
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#define AM335X_FB_H
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#if !CONFIG_IS_ENABLED(DM_VIDEO)
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#define HSVS_CONTROL BIT(25) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* opposite edges of pixel clock than
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* the lcd_pixel_o
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* 1 = lcd_lp and lcd_fp are driven
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* according to bit 24 Note that this
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* bit MUST be set to '0' for Passive
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* Matrix displays the edge timing is
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* fixed
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*/
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#define HSVS_RISEFALL BIT(24) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* the rising edge of pixel clock (bit
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* 25 must be set to 1)
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* 1 = lcd_lp and lcd_fp are driven on
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* the falling edge of pixel clock (bit
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* 25 must be set to 1)
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*/
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#define DE_INVERT BIT(23) /*
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* 0 = DE is low-active
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* 1 = DE is high-active
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*/
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#define PXCLK_INVERT BIT(22) /*
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* 0 = pix-clk is high-active
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* 1 = pic-clk is low-active
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*/
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#define HSYNC_INVERT BIT(21) /*
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* 0 = HSYNC is active high
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* 1 = HSYNC is avtive low
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*/
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#define VSYNC_INVERT BIT(20) /*
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* 0 = VSYNC is active high
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* 1 = VSYNC is active low
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*/
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struct am335x_lcdpanel {
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unsigned int hactive; /* Horizontal active area */
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unsigned int vactive; /* Vertical active area */
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unsigned int bpp; /* bits per pixel */
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unsigned int hfp; /* Horizontal front porch */
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unsigned int hbp; /* Horizontal back porch */
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unsigned int hsw; /* Horizontal Sync Pulse Width */
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unsigned int vfp; /* Vertical front porch */
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unsigned int vbp; /* Vertical back porch */
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unsigned int vsw; /* Vertical Sync Pulse Width */
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unsigned int pxl_clk; /* Pixel clock */
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unsigned int pol; /* polarity of sync, clock signals */
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unsigned int pup_delay; /*
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* time in ms after power on to
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* initialization of lcd-controller
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* (VCC ramp up time)
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*/
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unsigned int pon_delay; /*
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* time in ms after initialization of
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* lcd-controller (pic stabilization)
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*/
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void (*panel_power_ctrl)(int); /* fp for power on/off display */
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};
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int am335xfb_init(struct am335x_lcdpanel *panel);
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#else /* CONFIG_DM_VIDEO */
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/**
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* tilcdc_panel_info: Panel parameters
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*
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* @ac_bias: AC Bias Pin Frequency
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* @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt
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* @dma_burst_sz: DMA burst size
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* @bpp: Bits per pixel
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* @fdd: FIFO DMA Request Delay
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* @tft_alt_mode: TFT Alternative Signal Mapping (Only for active)
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* @invert_pxl_clk: Invert pixel clock
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* @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
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* @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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* @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
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* @fifo_th: DMA FIFO threshold
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*/
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struct tilcdc_panel_info {
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u32 ac_bias;
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u32 ac_bias_intrpt;
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u32 dma_burst_sz;
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u32 bpp;
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u32 fdd;
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bool tft_alt_mode;
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bool invert_pxl_clk;
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u32 sync_edge;
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u32 sync_ctrl;
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u32 raster_order;
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u32 fifo_th;
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};
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#endif /* CONFIG_DM_VIDEO */
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#endif /* AM335X_FB_H */
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