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41793000d7
Add rk3328 clock driver and cru structure definition. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
70 lines
1.4 KiB
C
70 lines
1.4 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CRU_RK3328_H_
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#define __ASM_ARCH_CRU_RK3328_H_
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#include <common.h>
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struct rk3328_clk_priv {
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struct rk3328_cru *cru;
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ulong rate;
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};
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struct rk3328_cru {
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u32 apll_con[5];
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u32 reserved1[3];
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u32 dpll_con[5];
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u32 reserved2[3];
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u32 cpll_con[5];
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u32 reserved3[3];
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u32 gpll_con[5];
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u32 reserved4[3];
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u32 mode_con;
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u32 misc;
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u32 reserved5[2];
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u32 glb_cnt_th;
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u32 glb_rst_st;
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u32 glb_srst_snd_value;
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u32 glb_srst_fst_value;
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u32 npll_con[5];
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u32 reserved6[(0x100 - 0xb4) / 4];
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u32 clksel_con[53];
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u32 reserved7[(0x200 - 0x1d4) / 4];
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u32 clkgate_con[29];
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u32 reserved8[3];
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u32 ssgtbl[32];
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u32 softrst_con[12];
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u32 reserved9[(0x380 - 0x330) / 4];
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u32 sdmmc_con[2];
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u32 sdio_con[2];
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u32 emmc_con[2];
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u32 sdmmc_ext_con[2];
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};
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check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (576 * MHz)
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#define CPLL_HZ (594 * MHz)
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#define CLK_CORE_HZ (600 * MHz)
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#define ACLKM_CORE_HZ (300 * MHz)
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#define PCLK_DBG_HZ (300 * MHz)
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#define PERIHP_ACLK_HZ (144000 * KHz)
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#define PERIHP_HCLK_HZ (72000 * KHz)
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#define PERIHP_PCLK_HZ (72000 * KHz)
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#define PWM_CLOCK_HZ (74 * MHz)
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enum apll_frequencies {
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APLL_816_MHZ,
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APLL_600_MHZ,
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};
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#endif /* __ASM_ARCH_CRU_RK3328_H_ */
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