mirror of
https://github.com/AsahiLinux/u-boot
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feede8b070
The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card. The 8572, 8536, and 8544 DS boards were modified to call this function. Code idea taken from Liu Yu <yu.liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
593 lines
14 KiB
C
593 lines
14 KiB
C
/*
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <tsec.h>
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#include "../common/pixis.h"
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#include "../common/sgmii_riser.h"
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long int fixed_sdram(void);
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int checkboard (void)
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{
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printf ("Board: MPC8572DS, System ID: 0x%02x, "
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"System Version: 0x%02x, FPGA Version: 0x%02x\n",
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in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
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in8(PIXIS_BASE + PIXIS_PVER));
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing....");
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_ddr_t *ddr= &immap->im_ddr;
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uint d_init;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
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ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
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ddr->err_sbe = CONFIG_SYS_DDR_SBE;
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#endif
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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return 512 * 1024 * 1024;
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}
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno=0;
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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printf (" eTSEC1 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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printf (" eTSEC2 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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printf (" eTSEC3 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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printf (" eTSEC4 is in sgmii mode.\n");
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#ifdef CONFIG_PCIE3
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
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struct pci_controller *hose = &pcie3_hose;
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int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
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(host_agent == 5) || (host_agent == 6);
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int pcie_configured = (io_sel == 0x7);
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struct pci_region *r = hose->regions;
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u32 temp32;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
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printf ("\n PCIE3 connected to ULI as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BUS,
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CONFIG_SYS_PCIE3_MEM_PHYS,
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CONFIG_SYS_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_IO_BUS,
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CONFIG_SYS_PCIE3_IO_PHYS,
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CONFIG_SYS_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE3 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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* Device 1d has the first on-board memory BAR.
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*/
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pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
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PCI_BASE_ADDRESS_1, &temp32);
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if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
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void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
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temp32, 4, 0);
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debug(" uli1572 read to %p\n", p);
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in_be32(p);
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}
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} else {
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printf (" PCIE3: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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struct pci_controller *hose = &pcie2_hose;
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int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
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(host_agent == 6) || (host_agent == 0);
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int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
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printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BUS,
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CONFIG_SYS_PCIE2_MEM_PHYS,
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CONFIG_SYS_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_IO_BUS,
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CONFIG_SYS_PCIE2_IO_PHYS,
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CONFIG_SYS_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE2 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
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(host_agent == 5);
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int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
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(io_sel == 0x7) || (io_sel == 0xb) ||
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(io_sel == 0xc) || (io_sel == 0xf);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BUS,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BUS,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = 2;
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
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return 0;
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}
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#ifdef CONFIG_GET_CLK_FROM_ICS307
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/* decode S[0-2] to Output Divider (OD) */
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static unsigned char ics307_S_to_OD[] = {
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10, 2, 8, 4, 5, 7, 3, 6
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};
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/* Calculate frequency being generated by ICS307-02 clock chip based upon
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* the control bytes being programmed into it. */
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/* XXX: This function should probably go into a common library */
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static unsigned long
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ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
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{
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const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
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unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
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unsigned long RDW = cw2 & 0x7F;
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unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
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unsigned long freq;
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/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
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/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
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* cw1: V8 V7 V6 V5 V4 V3 V2 V1
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* cw2: V0 R6 R5 R4 R3 R2 R1 R0
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*
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* R6:R0 = Reference Divider Word (RDW)
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* V8:V0 = VCO Divider Word (VDW)
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* S2:S0 = Output Divider Select (OD)
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* F1:F0 = Function of CLK2 Output
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* TTL = duty cycle
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* C1:C0 = internal load capacitance for cyrstal
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*/
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/* Adding 1 to get a "nicely" rounded number, but this needs
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* more tweaking to get a "properly" rounded number. */
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freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
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debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
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freq);
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return freq;
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}
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unsigned long get_board_sys_clk(ulong dummy)
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{
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return ics307_clk_freq (
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in8(PIXIS_BASE + PIXIS_VSYSCLK0),
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in8(PIXIS_BASE + PIXIS_VSYSCLK1),
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in8(PIXIS_BASE + PIXIS_VSYSCLK2)
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);
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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return ics307_clk_freq (
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in8(PIXIS_BASE + PIXIS_VDDRCLK0),
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in8(PIXIS_BASE + PIXIS_VDDRCLK1),
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in8(PIXIS_BASE + PIXIS_VDDRCLK2)
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);
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}
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#else
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unsigned long get_board_sys_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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i = in8(PIXIS_BASE + PIXIS_SPD);
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33333333;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66666666;
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break;
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case 4:
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val = 83333333;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 133333333;
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break;
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case 7:
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val = 166666666;
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break;
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}
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return val;
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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|
{
|
|
u8 i;
|
|
ulong val = 0;
|
|
|
|
i = in8(PIXIS_BASE + PIXIS_SPD);
|
|
i &= 0x38;
|
|
i >>= 3;
|
|
|
|
switch (i) {
|
|
case 0:
|
|
val = 33333333;
|
|
break;
|
|
case 1:
|
|
val = 40000000;
|
|
break;
|
|
case 2:
|
|
val = 50000000;
|
|
break;
|
|
case 3:
|
|
val = 66666666;
|
|
break;
|
|
case 4:
|
|
val = 83333333;
|
|
break;
|
|
case 5:
|
|
val = 100000000;
|
|
break;
|
|
case 6:
|
|
val = 133333333;
|
|
break;
|
|
case 7:
|
|
val = 166666666;
|
|
break;
|
|
}
|
|
return val;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_TSEC_ENET
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
struct tsec_info_struct tsec_info[4];
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
int num = 0;
|
|
|
|
#ifdef CONFIG_TSEC1
|
|
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
|
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
|
|
tsec_info[num].flags |= TSEC_SGMII;
|
|
num++;
|
|
#endif
|
|
#ifdef CONFIG_TSEC2
|
|
SET_STD_TSEC_INFO(tsec_info[num], 2);
|
|
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
|
|
tsec_info[num].flags |= TSEC_SGMII;
|
|
num++;
|
|
#endif
|
|
#ifdef CONFIG_TSEC3
|
|
SET_STD_TSEC_INFO(tsec_info[num], 3);
|
|
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
|
|
tsec_info[num].flags |= TSEC_SGMII;
|
|
num++;
|
|
#endif
|
|
#ifdef CONFIG_TSEC4
|
|
SET_STD_TSEC_INFO(tsec_info[num], 4);
|
|
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
|
|
tsec_info[num].flags |= TSEC_SGMII;
|
|
num++;
|
|
#endif
|
|
|
|
if (!num) {
|
|
printf("No TSECs initialized\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_SGMII_RISER
|
|
fsl_sgmii_riser_init(tsec_info, num);
|
|
#endif
|
|
|
|
tsec_eth_init(bis, tsec_info, num);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
|
struct pci_controller *hose);
|
|
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
phys_addr_t base;
|
|
phys_size_t size;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
base = getenv_bootm_low();
|
|
size = getenv_bootm_size();
|
|
|
|
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
|
|
|
#ifdef CONFIG_PCIE3
|
|
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE2
|
|
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE1
|
|
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
|
#endif
|
|
#ifdef CONFIG_FSL_SGMII_RISER
|
|
fsl_sgmii_riser_fdt_fixup(blob);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MP
|
|
extern void cpu_mp_lmb_reserve(struct lmb *lmb);
|
|
|
|
void board_lmb_reserve(struct lmb *lmb)
|
|
{
|
|
cpu_mp_lmb_reserve(lmb);
|
|
}
|
|
#endif
|