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367ea426a5
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
33 lines
1.1 KiB
Text
33 lines
1.1 KiB
Text
Qualcomm QUP SPI controller Device Tree Bindings
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Required properties:
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- compatible : Should be "qcom,spi-qup-v1.1.1", "qcom,spi-qup-v2.1.1"
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or "qcom,spi-qup-v2.2.1"
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- reg : Physical base address and size of SPI registers map.
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- clock : Clock phandle (see clock bindings for details).
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- #address-cells : Number of cells required to define a chip select
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address on the SPI bus. Should be set to 1.
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- #size-cells : Should be zero.
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- pinctrl-names : Must be "default"
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- pinctrl-n : At least one pinctrl phandle
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- cs-gpios : Should specify GPIOs used for chipselects.
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The gpios will be referred to as reg = <index> in the
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SPI child nodes.
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Optional properties:
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- num-cs : total number of chipselects
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Example:
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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clock = <&gcc 23>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "spi";
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pinctrl-0 = <&blsp_spi0>;
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num-cs = <2>;
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cs-gpios = <&soc_gpios 54 GPIO_ACTIVE_HIGH>, <&soc_gpios 4 GPIO_ACTIVE_HIGH>;
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};
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