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e7005b3e80
Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
34 lines
1.2 KiB
Text
34 lines
1.2 KiB
Text
Freescale ColdFire DSPI controller
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Required properties:
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- compatible : "fsl,mcf-dspi"
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- #address-cells: <1>, as required by generic SPI binding
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- #size-cells: <0>, also as required by generic SPI binding
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- reg : offset and length of the register set for the device
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Optional properties:
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- spi-max-frequency : max supported spi frequency
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- num-cs : the number of the chipselect signals
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- spi-mode: spi motorola mode, 0 to 3
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- ctar-params: CTAR0 to 7 register configuration, as an array
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of 8 integer fields for each register, where each register
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is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
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- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
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select and the start of clock signal, at the start of a transfer.
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- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
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signal and deactivating chip select, at the end of a transfer.
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Example:
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dspi0: dspi@fc05c000 {
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compatible = "fsl,mcf-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfc05c000 0x100>;
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spi-max-frequency = <50000000>;
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num-cs = <4>;
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spi-mode = <0>;
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ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
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<7, 0, 0, 0, 0, 0, 1, 6>,
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<7, 0, 0, 0, 0, 0, 1, 6>;
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};
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