mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 00:33:06 +00:00
345b77baca
As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
172 lines
6.4 KiB
C
172 lines
6.4 KiB
C
/*
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* Configuration for AMCC 460SX Ref (redwood)
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*
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* (C) Copyright 2008
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* Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_440 1 /* ... PPC460 family */
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#define CONFIG_460SX 1 /* ... PPC460 family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_SYS_TEXT_BASE 0xfffb0000
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/*-----------------------------------------------------------------------
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* Include common defines/options for all AMCC boards
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*----------------------------------------------------------------------*/
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#define CONFIG_HOSTNAME redwood
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#include "amcc-common.h"
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
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#define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
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#define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
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#define CONFIG_SYS_PCIE_MEMSIZE 0x01000000
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000
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#define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000
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#define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000
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#define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000
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#define CONFIG_SYS_PCIE2_CFGBASE 0xba000000
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/* PCIe mapped UTL registers */
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#define CONFIG_SYS_PCIE0_REGBASE 0xd0000000
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#define CONFIG_SYS_PCIE1_REGBASE 0xd0010000
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#define CONFIG_SYS_PCIE2_REGBASE 0xd0020000
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
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#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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#define CONFIG_SYS_SPD_MAX_DIMMS 2
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/* SPD i2c spd addresses */
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#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
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#define IIC0_DIMM0_ADDR 0x53
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#define IIC0_DIMM1_ADDR 0x52
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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#define IIC0_BOOTPROM_ADDR 0x50
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#define IIC0_ALT_BOOTPROM_ADDR 0x54
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/* Don't probe these addrs */
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
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#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
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#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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""
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/*----------------------------------------------------------------------------+
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| Commands in addition to amcc-common.h
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+----------------------------------------------------------------------------*/
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#define CONFIG_CMD_SDRAM
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_M88E1141_PHY 1 /* Enable phy */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR 0xfffa0000
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#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*---------------------------------------------------------------------------*/
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#endif /* __CONFIG_H */
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