mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 00:33:06 +00:00
505 lines
14 KiB
C
505 lines
14 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_LS102XA
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_DEEP_SLEEP
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#ifdef CONFIG_DEEP_SLEEP
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#define CONFIG_SILENT_CONSOLE
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#endif
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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/*
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* USB
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*/
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/*
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* EHCI Support - disbaled by default as
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* there is no signal coming out of soc on
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* this board for this controller. However,
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* the silicon still has this controller,
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* and anyone can use this controller by
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* taking signals out on their board.
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*/
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/*#define CONFIG_HAS_FSL_DR_USB*/
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#ifdef CONFIG_HAS_FSL_DR_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#endif
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/* XHCI Support - enabled by default */
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_XHCI_FSL
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#endif
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#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
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#define CONFIG_USB_STORAGE
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#endif
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/*
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* Generic Timer Definitions
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*/
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#define GENERIC_TIMER_CLK 12500000
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define DDR_SDRAM_CFG 0x470c0008
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#define DDR_CS0_BNDS 0x008000bf
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#define DDR_CS0_CONFIG 0x80014302
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#define DDR_TIMING_CFG_0 0x50550004
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#define DDR_TIMING_CFG_1 0xbcb38c56
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#define DDR_TIMING_CFG_2 0x0040d120
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#define DDR_TIMING_CFG_3 0x010e1000
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#define DDR_TIMING_CFG_4 0x00000001
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#define DDR_TIMING_CFG_5 0x03401400
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#define DDR_SDRAM_CFG_2 0x00401010
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#define DDR_SDRAM_MODE 0x00061c60
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#define DDR_SDRAM_MODE_2 0x00180000
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#define DDR_SDRAM_INTERVAL 0x18600618
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#define DDR_DDR_WRLVL_CNTL 0x8655f605
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#define DDR_DDR_WRLVL_CNTL_2 0x05060607
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#define DDR_DDR_WRLVL_CNTL_3 0x05050505
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#define DDR_DDR_CDR1 0x80040000
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#define DDR_DDR_CDR2 0x00000001
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#define DDR_SDRAM_CLK_CNTL 0x02000000
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#define DDR_DDR_ZQ_CNTL 0x89080600
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#define DDR_CS0_CONFIG_2 0
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#define DDR_SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
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#define SDRAM_CFG2_FRC_SR 0x80000000
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#define SDRAM_CFG_BI 0x00000001
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
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#endif
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#ifdef CONFIG_SD_BOOT
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#ifdef CONFIG_SD_BOOT_QSPI
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
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#else
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
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#endif
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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#define CONFIG_SYS_TEXT_BASE 0x82000000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#endif
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_TEXT_BASE 0x40010000
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#endif
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_NO_FLASH
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0x60100000
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#endif
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_HAS_SERDES
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#define CONFIG_FSL_CAAM /* Enable CAAM */
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
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!defined(CONFIG_QSPI_BOOT)
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#define CONFIG_U_QE
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#endif
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/*
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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/* NOR Flash Timing Params */
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TAVDS(0x0) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1A) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWP(0x1c) | \
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FTIM2_NOR_TWPH(0x0e))
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#define CONFIG_SYS_NOR_FTIM3 0
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#endif
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/* CPLD */
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#define CONFIG_SYS_CPLD_BASE 0x7fb00000
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#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
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#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
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#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/* CPLD Timing parameters for IFC GPCM */
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#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
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FTIM0_GPCM_TEADC(0xf) | \
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FTIM0_GPCM_TEAHC(0xf))
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#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0xff))
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#define CONFIG_SYS_FPGA_FTIM3 0x0
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
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/*
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* Serial Port
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*/
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#ifdef CONFIG_LPUART
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#define CONFIG_LPUART_32B_REG
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#else
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#endif
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#define CONFIG_BAUDRATE 115200
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/*
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* MMC
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*/
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#define CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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/* SPI */
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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/* QSPI */
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#define QSPI0_AMBA_BASE 0x40000000
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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/* DSPI */
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#endif
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/* DM SPI */
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#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
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#define CONFIG_DM_SPI_FLASH
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#endif
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/*
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* Video
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*/
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#define CONFIG_FSL_DCU_FB
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#ifdef CONFIG_FSL_DCU_FB
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#define CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_FSL_DCU_SII9022A
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#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
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#define CONFIG_SYS_I2C_DVI_ADDR 0x39
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#endif
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/*
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* eTSEC
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*/
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#define CONFIG_TSEC_ENET
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_MII
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#define CONFIG_MII_DEFAULT_TSEC 1
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#endif
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/* PCIe */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CONFIG_SYS_PCI_64BIT
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#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
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#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
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#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
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#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
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#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
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#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI
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#endif
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_ARMV7_NONSEC
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#define CONFIG_ARMV7_VIRT
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_TIMER_CLK_FREQ 12500000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define CONFIG_FSL_DEVICE_DISABLE
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#define CONFIG_BOOTDELAY 3
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#ifdef CONFIG_LPUART
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_high=0xffffffff\0"
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#else
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_high=0xffffffff\0"
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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#define CONFIG_LS102XA_STREAM_ID
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/*
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* Stack sizes
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (30 * 1024)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_SD_BOOT)
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x20000
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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#define CONFIG_MISC_INIT_R
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/* Hash command with SHA acceleration supported in hardware */
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#ifdef CONFIG_FSL_CAAM
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#define CONFIG_CMD_HASH
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#define CONFIG_SHA_HW_ACCEL
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#endif
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#include <asm/fsl_secure_boot.h>
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#endif
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