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aafa64827f
There is off-by-one error in sandbox_emul_gpio that causes segfault of certain tests. EMUL_GPIO_REG_END is the address of last valid (emulated) register. This patch fixed this (by adding one more element to emulated register array). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
/*
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* Sample SPMI bus driver
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*
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* It emulates bus with single pm8916-like pmic that has only GPIO reigsters.
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <spmi/spmi.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define EMUL_GPIO_PID_START 0xC0
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#define EMUL_GPIO_PID_END 0xC3
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#define EMUL_GPIO_COUNT 4
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#define EMUL_GPIO_REG_END 0x46 /* Last valid register */
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#define EMUL_PERM_R 0x1
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#define EMUL_PERM_W 0x2
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#define EMUL_PERM_RW (EMUL_PERM_R | EMUL_PERM_W)
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struct sandbox_emul_fake_regs {
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u8 value;
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u8 access_mask;
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u8 perms; /* Access permissions */
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};
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struct sandbox_emul_gpio {
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/* Fake registers - need one more entry as REG_END is valid address. */
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struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END + 1];
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};
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struct sandbox_spmi_priv {
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struct sandbox_emul_gpio gpios[EMUL_GPIO_COUNT];
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};
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/* Check if valid register was requested */
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static bool check_address_valid(int usid, int pid, int off)
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{
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if (usid != 0)
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return false;
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if (pid < EMUL_GPIO_PID_START || pid > EMUL_GPIO_PID_END)
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return false;
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if (off > EMUL_GPIO_REG_END)
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return false;
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return true;
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}
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static int sandbox_spmi_write(struct udevice *dev, int usid, int pid, int off,
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uint8_t val)
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{
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struct sandbox_spmi_priv *priv = dev_get_priv(dev);
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struct sandbox_emul_fake_regs *regs;
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if (!check_address_valid(usid, pid, off))
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return -EIO;
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regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */
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switch (off) {
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case 0x40: /* Control */
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val &= regs[off].access_mask;
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if (((val & 0x30) == 0x10) || ((val & 0x30) == 0x20)) {
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/* out/inout - set status register */
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regs[0x8].value &= ~0x1;
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regs[0x8].value |= val & 0x1;
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}
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break;
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default:
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if (regs[off].perms & EMUL_PERM_W)
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regs[off].value = val & regs[off].access_mask;
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}
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return 0;
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}
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static int sandbox_spmi_read(struct udevice *dev, int usid, int pid, int off)
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{
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struct sandbox_spmi_priv *priv = dev_get_priv(dev);
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struct sandbox_emul_fake_regs *regs;
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if (!check_address_valid(usid, pid, off))
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return -EIO;
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regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */
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if (regs[0x46].value == 0) /* Block disabled */
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return 0;
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switch (off) {
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case 0x8: /* Status */
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if (regs[0x46].value == 0) /* Block disabled */
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return 0;
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return regs[off].value;
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default:
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if (regs[off].perms & EMUL_PERM_R)
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return regs[off].value;
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else
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return 0;
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}
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}
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static struct dm_spmi_ops sandbox_spmi_ops = {
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.read = sandbox_spmi_read,
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.write = sandbox_spmi_write,
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};
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static int sandbox_spmi_probe(struct udevice *dev)
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{
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struct sandbox_spmi_priv *priv = dev_get_priv(dev);
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int i;
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for (i = 0; i < EMUL_GPIO_COUNT; ++i) {
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struct sandbox_emul_fake_regs *regs = priv->gpios[i].r;
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regs[4].perms = EMUL_PERM_R;
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regs[4].value = 0x10;
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regs[5].perms = EMUL_PERM_R;
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regs[5].value = 0x5;
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regs[8].access_mask = 0x81;
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regs[8].perms = EMUL_PERM_RW;
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regs[0x40].access_mask = 0x7F;
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regs[0x40].perms = EMUL_PERM_RW;
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regs[0x41].access_mask = 7;
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regs[0x41].perms = EMUL_PERM_RW;
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regs[0x42].access_mask = 7;
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regs[0x42].perms = EMUL_PERM_RW;
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regs[0x42].value = 0x4;
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regs[0x45].access_mask = 0x3F;
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regs[0x45].perms = EMUL_PERM_RW;
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regs[0x45].value = 0x1;
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regs[0x46].access_mask = 0x80;
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regs[0x46].perms = EMUL_PERM_RW;
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regs[0x46].value = 0x80;
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}
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return 0;
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}
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static const struct udevice_id sandbox_spmi_ids[] = {
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{ .compatible = "sandbox,spmi" },
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{ }
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};
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U_BOOT_DRIVER(msm_spmi) = {
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.name = "sandbox_spmi",
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.id = UCLASS_SPMI,
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.of_match = sandbox_spmi_ids,
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.ops = &sandbox_spmi_ops,
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.probe = sandbox_spmi_probe,
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.priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv),
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};
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