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341e548eb8
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
286 lines
5 KiB
Text
286 lines
5 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 - 2021 Marvell International Ltd.
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*/
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/*
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* Device Tree file for Marvell Armada 8040 Development board platform
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*/
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#include "armada-8040.dtsi"
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/ {
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model = "Marvell Armada 8040 DB board";
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compatible = "marvell,armada8040-db", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &cp0_i2c0;
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spi0 = &cp1_spi1;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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/* Accessible over the mini-USB CON9 connector on the main board */
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&uart0 {
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status = "okay";
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};
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&ap_pinctl {
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/* MPP Bus:
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* SDIO [0-10]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 1 1 1 1
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1 3 0 0 0 0 0 0 0 3 >;
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};
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&ap_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ap_emmc_pins>;
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bus-width = <8>;
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status = "okay";
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};
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&cp0_pinctl {
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/* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32,34] GE_MDIO/MDC
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* [33] GPIO: GE_INT#/push button/Wake
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* [35] MSS_GPIO[3]: MSS_PWDN
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* [36] MSS_GPIO[5]: MSS_VTT_EN
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* [37-38] I2C0
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* [39] PTP_CLK
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* [40-41] SATA[0/1]_PRESENT_ACTIVEn
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* [42-43] XG_MDC/XG_MDIO (XSMI)
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* [44-55] RGMII1
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* [56-62] SD
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5
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0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
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0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
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0xe 0xe 0xe>;
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};
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&cp0_comphy {
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/* Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: SATA0
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* Lane 2: SFI (10G)
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* Lane 3: SATA1
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* Lane 4: USB3_HOST1
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* Lane 5: PCIe2 (x1)
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_PEX2>;
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};
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};
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/* CON6 on CP0 expansion */
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&cp0_pcie0 {
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status = "okay";
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};
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&cp0_pcie1 {
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status = "disabled";
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};
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/* CON5 on CP0 expansion */
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&cp0_pcie2 {
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status = "okay";
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};
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&cp0_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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/* CON4 on CP0 expansion */
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&cp0_sata0 {
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status = "okay";
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};
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/* CON9 on CP0 expansion */
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&cp0_usb3_0 {
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status = "okay";
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};
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/* CON10 on CP0 expansion */
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&cp0_usb3_1 {
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status = "okay";
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};
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&cp0_utmi0 {
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status = "okay";
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};
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&cp0_utmi1 {
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status = "okay";
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};
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&cp0_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins>;
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bus-width = <4>;
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status = "okay";
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};
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&cp1_pinctl {
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/* MPP Bus:
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* [0-11] RGMII0
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* [13-16] SPI1
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* [27,31] GE_MDIO/MDC
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* [28] SATA1_PRESENT_ACTIVEn
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* [29-30] UART0
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* [32-62] = 0xff: Keep default CP1_shared_pins
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
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0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa
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0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff>;
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};
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&cp1_comphy {
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/* Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: SATA0
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* Lane 2: SFI (10G)
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* Lane 3: SATA1
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* Lane 4: PCIe1 (x1)
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* Lane 5: PCIe2 (x1)
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_PEX1>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_PEX2>;
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};
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};
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/* CON6 on CP1 expansion */
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&cp1_pcie0 {
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status = "okay";
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};
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&cp1_pcie1 {
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status = "okay";
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};
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/* CON5 on CP1 expansion */
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&cp1_pcie2 {
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status = "okay";
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};
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&cp1_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_spi1_pins>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xce0000>;
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};
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};
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};
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};
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/* CON4 on CP1 expansion */
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&cp1_sata0 {
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status = "okay";
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};
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/* CON9 on CP1 expansion */
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&cp1_usb3_0 {
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status = "okay";
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};
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/* CON10 on CP1 expansion */
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&cp1_usb3_1 {
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status = "okay";
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};
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&cp1_utmi0 {
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status = "okay";
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};
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&cp0_mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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