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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
173 lines
5 KiB
C
173 lines
5 KiB
C
/*
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* (C) Copyright 2003-2004
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* MPC Data Limited (http://www.mpc-data.co.uk)
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* Dave Peverley <dpeverley at mpc-data.co.uk>
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*
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* Configuation settings for the TI OMAP Perseus 2 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP730 1 /* which is in a 730 */
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#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
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/*
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* Input clock of PLL
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* The OMAP730 Perseus 2 has 13MHz input clock
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*/
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#define CONFIG_SYS_CLK_FREQ 13000000
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_LAN91C96
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#define CONFIG_LAN91C96_BASE 0x04000300
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#define CONFIG_LAN91C96_EXT_PHY
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (1)
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#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
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#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
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* on perseus */
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#include <configs/omap730.h>
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#include <configs/h2_p2_dbg_board.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
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#define CONFIG_LOADADDR 0x10000000
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#define CONFIG_ETHADDR
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.0.23
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#define CONFIG_SERVERIP 192.150.0.100
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#define CONFIG_BOOTFILE "uImage" /* File to load */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
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/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
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* the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
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* local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#if defined(CONFIG_CS0_BOOT)
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#define PHYS_FLASH_1 0x0C000000
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#elif defined(CONFIG_CS3_BOOT)
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#define PHYS_FLASH_1 0x00000000
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#else
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#error Unknown Boot Chip-Select number
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#endif
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#define PHYS_SRAM 0x20000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
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#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
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/* addr of environment */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
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#endif /* ! __CONFIG_H */
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