mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
2cb156e126
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC To add support for the i.MX8M Nano GW7902: - Add imx8mn-venice dts/defconfig/include - Add imx8mn-gw7902 dts - Add imx8mn-2gb lpddr4 dram configs - Add misc support for IMX8M Nano SoC - rename imx8mm-venice.c to venice.c as it is no longer imx8mm specific - update README with differences for IMX8MN vs IMX8MM Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#ifndef __IMX8MM_VENICE_H
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#define __IMX8MM_VENICE_H
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#include <asm/arch/imx-regs.h>
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#include <linux/sizes.h>
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#define CONFIG_SPL_MAX_SIZE (148 * 1024)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x980000
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#define CONFIG_SPL_BSS_START_ADDR 0x950000
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif
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#define MEM_LAYOUT_ENV_SETTINGS \
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"fdt_addr_r=0x44000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"ramdisk_addr_r=0x46400000\0" \
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"scriptaddr=0x46000000\0"
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/* Enable Distro Boot */
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 2) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#undef CONFIG_ISO_PARTITION
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#else
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#define BOOTENV
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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MEM_LAYOUT_ENV_SETTINGS \
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"script=boot.scr\0" \
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"bootm_size=0x10000000\0" \
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"dev=2\0" \
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"preboot=gsc wd-disable\0" \
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"console=ttymxc1,115200\0" \
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"update_firmware=" \
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"tftpboot $loadaddr $image && " \
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"setexpr blkcnt $filesize + 0x1ff && " \
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"setexpr blkcnt $blkcnt / 0x200 && " \
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"mmc dev $dev && " \
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"mmc write $loadaddr 0x40 $blkcnt\0" \
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"boot_net=" \
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"tftpboot $kernel_addr_r $image && " \
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"booti $kernel_addr_r - $fdtcontroladdr\0" \
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"update_rootfs=" \
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"tftpboot $loadaddr $image && " \
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"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
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"update_all=" \
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"tftpboot $loadaddr $image && " \
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"gzwrite mmc $dev $loadaddr $filesize\0" \
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"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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/* SDRAM configuration */
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_1G
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#define CONFIG_SYS_BOOTM_LEN SZ_256M
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/* UART */
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* USDHC */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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/* FEC */
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#define CONFIG_ETHPRIME "eth0"
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#endif
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