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126fe70d77
LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#ifdef CONFIG_FSL_DEEP_SLEEP
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#include <fsl_sleep.h>
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#endif
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 3) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = udimms[0];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found for %lu MT/s\n",
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ddr_freq);
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printf("Trying to use the highest speed (%u) parameters\n",
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pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
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popts->data_bus_width = 0; /* 64b data bus */
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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popts->bstopre = 0; /* enable auto precharge */
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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return fsl_ddr_sdram_size();
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#else
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puts("Initializing DDR....using SPD\n");
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dram_size = fsl_ddr_sdram();
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#endif
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#ifdef CONFIG_FSL_DEEP_SLEEP
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fsl_dp_ddr_restore();
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#endif
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erratum_a008850_post();
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return dram_size;
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}
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void dram_init_banksize(void)
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{
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/*
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* gd->arch.secure_ram tracks the location of secure memory.
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* It was set as if the memory starts from 0.
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* The address needs to add the offset of its bank.
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
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gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
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gd->bd->bi_dram[1].size = gd->ram_size -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[1].start +
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gd->arch.secure_ram -
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CONFIG_SYS_DDR_BLOCK1_SIZE;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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} else {
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gd->bd->bi_dram[0].size = gd->ram_size;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->arch.secure_ram = gd->bd->bi_dram[0].start +
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gd->arch.secure_ram;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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}
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}
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