mirror of
https://github.com/AsahiLinux/u-boot
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7b77b1f63b
Convert to using the common config files. Signed-off-by: Adam Ford <adam.ford@logicpd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
256 lines
7 KiB
C
256 lines
7 KiB
C
/*
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* (C) Copyright 2011
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* Logic Product Development <www.logicpd.com>
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*
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* Author :
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* Peter Barada <peter.barada@logicpd.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <netdev.h>
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#include <flash.h>
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#include <nand.h>
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#include <i2c.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include "omap3logic.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* two dimensional array of strucures containining board name and Linux
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* machine IDs; row it selected based on CPU column is slected based
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* on hsusb0_data5 pin having a pulldown resistor
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*/
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static const struct ns16550_platdata omap3logic_serial = {
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OMAP34XX_UART1,
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2,
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V_NS16550_CLK
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};
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U_BOOT_DEVICE(omap3logic_uart) = {
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"serial_omap",
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&omap3logic_serial
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};
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static struct board_id {
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char *name;
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int machine_id;
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} boards[2][2] = {
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{
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{
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.name = "OMAP35xx SOM LV",
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.machine_id = MACH_TYPE_OMAP3530_LV_SOM,
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},
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{
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.name = "OMAP35xx Torpedo",
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.machine_id = MACH_TYPE_OMAP3_TORPEDO,
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},
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},
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{
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{
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.name = "DM37xx SOM LV",
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.machine_id = MACH_TYPE_DM3730_SOM_LV,
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},
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{
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.name = "DM37xx Torpedo",
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.machine_id = MACH_TYPE_DM3730_TORPEDO,
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},
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},
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};
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/*
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* BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
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*/
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#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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struct board_id *board;
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unsigned int val;
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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/*
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* To identify between a SOM LV and Torpedo module,
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* a pulldown resistor is on hsusb0_data5 for the SOM LV module.
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* Drive the pin (and let it soak), then read it back.
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* If the pin is still high its a Torpedo. If low its a SOM LV
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*/
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/* Mux hsusb0_data5 as a GPIO */
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
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if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
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/*
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* Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
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* will drain the voltage.
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*/
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gpio_direction_output(BOARD_ID_GPIO, 0);
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gpio_set_value(BOARD_ID_GPIO, 1);
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/* Let it soak for a bit */
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sdelay(0x100);
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/*
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* Read state of BOARD_ID_GPIO as an input and if its set.
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* If so the board is a Torpedo
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*/
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gpio_direction_input(BOARD_ID_GPIO);
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val = gpio_get_value(BOARD_ID_GPIO);
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gpio_free(BOARD_ID_GPIO);
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board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
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printf("Board: %s\n", board->name);
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/* Set the machine_id passed to Linux */
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gd->bd->bi_arch_number = board->machine_id;
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}
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/* restore hsusb0_data5 pin as hsusb0_data5 */
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
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return 0;
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}
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_GENERIC_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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#ifdef CONFIG_SMC911X
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/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
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static const u32 gpmc_lan92xx_config[] = {
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NET_LAN92XX_GPMC_CONFIG1,
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NET_LAN92XX_GPMC_CONFIG2,
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NET_LAN92XX_GPMC_CONFIG3,
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NET_LAN92XX_GPMC_CONFIG4,
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NET_LAN92XX_GPMC_CONFIG5,
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NET_LAN92XX_GPMC_CONFIG6,
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};
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int board_eth_init(bd_t *bis)
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{
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enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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}
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#endif
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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/*GPMC*/
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
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MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
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/*Expansion card */
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MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
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/* Serial Console */
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MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
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MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
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/* I2C */
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MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
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MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
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MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
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MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
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MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
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/*Control and debug */
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MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
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MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
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}
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