mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
d055911887
Api is added to decode peripheral id based on the interrupt number of the peripheral. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
478 lines
12 KiB
C
478 lines
12 KiB
C
/*
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* Copyright (c) 2012 Samsung Electronics.
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* Abhilash Kesavan <a.kesavan@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/sromc.h>
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static void exynos5_uart_config(int peripheral)
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{
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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struct s5p_gpio_bank *bank;
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int i, start, count;
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switch (peripheral) {
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case PERIPH_ID_UART0:
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bank = &gpio1->a0;
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start = 0;
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count = 4;
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break;
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case PERIPH_ID_UART1:
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bank = &gpio1->d0;
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start = 0;
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count = 4;
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break;
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case PERIPH_ID_UART2:
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bank = &gpio1->a1;
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start = 0;
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count = 4;
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break;
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case PERIPH_ID_UART3:
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bank = &gpio1->a1;
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start = 4;
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count = 2;
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break;
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}
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for (i = start; i < start + count; i++) {
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s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
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s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
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}
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}
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static int exynos5_mmc_config(int peripheral, int flags)
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{
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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struct s5p_gpio_bank *bank, *bank_ext;
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int i, start = 0, gpio_func = 0;
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switch (peripheral) {
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case PERIPH_ID_SDMMC0:
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bank = &gpio1->c0;
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bank_ext = &gpio1->c1;
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start = 0;
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gpio_func = GPIO_FUNC(0x2);
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break;
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case PERIPH_ID_SDMMC1:
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bank = &gpio1->c2;
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bank_ext = NULL;
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break;
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case PERIPH_ID_SDMMC2:
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bank = &gpio1->c3;
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bank_ext = &gpio1->c4;
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start = 3;
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gpio_func = GPIO_FUNC(0x3);
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break;
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case PERIPH_ID_SDMMC3:
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bank = &gpio1->c4;
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bank_ext = NULL;
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break;
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}
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if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
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debug("SDMMC device %d does not support 8bit mode",
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peripheral);
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return -1;
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}
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if (flags & PINMUX_FLAG_8BIT_MODE) {
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for (i = start; i <= (start + 3); i++) {
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s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
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s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
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s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
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}
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}
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for (i = 0; i < 2; i++) {
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s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
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s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
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s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
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}
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for (i = 3; i <= 6; i++) {
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s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
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s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
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s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
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}
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return 0;
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}
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static void exynos5_sromc_config(int flags)
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{
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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int i;
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/*
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* SROM:CS1 and EBI
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*
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* GPY0[0] SROM_CSn[0]
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* GPY0[1] SROM_CSn[1](2)
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* GPY0[2] SROM_CSn[2]
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* GPY0[3] SROM_CSn[3]
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* GPY0[4] EBI_OEn(2)
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* GPY0[5] EBI_EEn(2)
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*
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* GPY1[0] EBI_BEn[0](2)
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* GPY1[1] EBI_BEn[1](2)
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* GPY1[2] SROM_WAIT(2)
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* GPY1[3] EBI_DATA_RDn(2)
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*/
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s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
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GPIO_FUNC(2));
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s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
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s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
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for (i = 0; i < 4; i++)
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s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
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/*
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* EBI: 8 Addrss Lines
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*
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* GPY3[0] EBI_ADDR[0](2)
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* GPY3[1] EBI_ADDR[1](2)
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* GPY3[2] EBI_ADDR[2](2)
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* GPY3[3] EBI_ADDR[3](2)
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* GPY3[4] EBI_ADDR[4](2)
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* GPY3[5] EBI_ADDR[5](2)
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* GPY3[6] EBI_ADDR[6](2)
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* GPY3[7] EBI_ADDR[7](2)
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*
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* EBI: 16 Data Lines
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*
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* GPY5[0] EBI_DATA[0](2)
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* GPY5[1] EBI_DATA[1](2)
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* GPY5[2] EBI_DATA[2](2)
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* GPY5[3] EBI_DATA[3](2)
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* GPY5[4] EBI_DATA[4](2)
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* GPY5[5] EBI_DATA[5](2)
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* GPY5[6] EBI_DATA[6](2)
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* GPY5[7] EBI_DATA[7](2)
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*
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* GPY6[0] EBI_DATA[8](2)
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* GPY6[1] EBI_DATA[9](2)
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* GPY6[2] EBI_DATA[10](2)
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* GPY6[3] EBI_DATA[11](2)
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* GPY6[4] EBI_DATA[12](2)
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* GPY6[5] EBI_DATA[13](2)
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* GPY6[6] EBI_DATA[14](2)
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* GPY6[7] EBI_DATA[15](2)
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*/
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for (i = 0; i < 8; i++) {
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s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
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s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
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s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
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s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
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s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
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s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
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}
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}
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static void exynos5_i2c_config(int peripheral, int flags)
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{
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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switch (peripheral) {
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case PERIPH_ID_I2C0:
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s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
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s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
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break;
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case PERIPH_ID_I2C1:
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s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
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s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
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break;
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case PERIPH_ID_I2C2:
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s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C3:
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s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C4:
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s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C5:
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s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C6:
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s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
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s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
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break;
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case PERIPH_ID_I2C7:
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s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
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break;
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}
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}
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static void exynos5_i2s_config(int peripheral)
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{
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int i;
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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for (i = 0; i < 5; i++)
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s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
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}
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void exynos5_spi_config(int peripheral)
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{
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int cfg = 0, pin = 0, i;
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struct s5p_gpio_bank *bank = NULL;
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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struct exynos5_gpio_part2 *gpio2 =
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(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
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switch (peripheral) {
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case PERIPH_ID_SPI0:
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bank = &gpio1->a2;
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cfg = GPIO_FUNC(0x2);
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pin = 0;
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break;
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case PERIPH_ID_SPI1:
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bank = &gpio1->a2;
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cfg = GPIO_FUNC(0x2);
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pin = 4;
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break;
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case PERIPH_ID_SPI2:
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bank = &gpio1->b1;
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cfg = GPIO_FUNC(0x5);
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pin = 1;
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break;
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case PERIPH_ID_SPI3:
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bank = &gpio2->f1;
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cfg = GPIO_FUNC(0x2);
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pin = 0;
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break;
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case PERIPH_ID_SPI4:
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for (i = 0; i < 2; i++) {
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s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
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s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
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}
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break;
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}
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if (peripheral != PERIPH_ID_SPI4) {
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for (i = pin; i < pin + 4; i++)
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s5p_gpio_cfg_pin(bank, i, cfg);
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}
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}
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static int exynos5_pinmux_config(int peripheral, int flags)
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{
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switch (peripheral) {
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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case PERIPH_ID_UART3:
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exynos5_uart_config(peripheral);
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break;
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case PERIPH_ID_SDMMC0:
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case PERIPH_ID_SDMMC1:
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case PERIPH_ID_SDMMC2:
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case PERIPH_ID_SDMMC3:
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return exynos5_mmc_config(peripheral, flags);
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case PERIPH_ID_SROMC:
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exynos5_sromc_config(flags);
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break;
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case PERIPH_ID_I2C0:
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case PERIPH_ID_I2C1:
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case PERIPH_ID_I2C2:
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case PERIPH_ID_I2C3:
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case PERIPH_ID_I2C4:
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case PERIPH_ID_I2C5:
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case PERIPH_ID_I2C6:
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case PERIPH_ID_I2C7:
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exynos5_i2c_config(peripheral, flags);
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break;
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case PERIPH_ID_I2S1:
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exynos5_i2s_config(peripheral);
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break;
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case PERIPH_ID_SPI0:
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case PERIPH_ID_SPI1:
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case PERIPH_ID_SPI2:
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case PERIPH_ID_SPI3:
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case PERIPH_ID_SPI4:
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exynos5_spi_config(peripheral);
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break;
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default:
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debug("%s: invalid peripheral %d", __func__, peripheral);
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return -1;
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}
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return 0;
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}
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static void exynos4_i2c_config(int peripheral, int flags)
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{
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struct exynos4_gpio_part1 *gpio1 =
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(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
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switch (peripheral) {
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case PERIPH_ID_I2C0:
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s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
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s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
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break;
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case PERIPH_ID_I2C1:
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s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
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s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
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break;
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case PERIPH_ID_I2C2:
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s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C3:
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s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C4:
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s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C5:
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s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
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break;
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case PERIPH_ID_I2C6:
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s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
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s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
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break;
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case PERIPH_ID_I2C7:
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s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
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s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
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break;
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}
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}
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static int exynos4_mmc_config(int peripheral, int flags)
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{
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struct exynos4_gpio_part2 *gpio2 =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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struct s5p_gpio_bank *bank, *bank_ext;
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int i;
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switch (peripheral) {
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case PERIPH_ID_SDMMC0:
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bank = &gpio2->k0;
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bank_ext = &gpio2->k1;
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break;
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case PERIPH_ID_SDMMC2:
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bank = &gpio2->k2;
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bank_ext = &gpio2->k3;
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break;
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default:
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return -1;
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}
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for (i = 0; i < 7; i++) {
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if (i == 2)
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continue;
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s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
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s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
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s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
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}
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if (flags & PINMUX_FLAG_8BIT_MODE) {
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for (i = 3; i < 7; i++) {
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s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
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s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
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s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
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}
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}
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return 0;
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}
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static int exynos4_pinmux_config(int peripheral, int flags)
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{
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switch (peripheral) {
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case PERIPH_ID_I2C0:
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case PERIPH_ID_I2C1:
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case PERIPH_ID_I2C2:
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case PERIPH_ID_I2C3:
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case PERIPH_ID_I2C4:
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case PERIPH_ID_I2C5:
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case PERIPH_ID_I2C6:
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case PERIPH_ID_I2C7:
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exynos4_i2c_config(peripheral, flags);
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break;
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case PERIPH_ID_SDMMC0:
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case PERIPH_ID_SDMMC2:
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return exynos4_mmc_config(peripheral, flags);
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case PERIPH_ID_SDMMC1:
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case PERIPH_ID_SDMMC3:
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case PERIPH_ID_SDMMC4:
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printf("SDMMC device %d not implemented\n", peripheral);
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return -1;
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default:
|
|
debug("%s: invalid peripheral %d", __func__, peripheral);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_pinmux_config(int peripheral, int flags)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
return exynos5_pinmux_config(peripheral, flags);
|
|
else if (cpu_is_exynos4())
|
|
return exynos4_pinmux_config(peripheral, flags);
|
|
else {
|
|
debug("pinmux functionality not supported\n");
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_OF_CONTROL
|
|
static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
|
|
{
|
|
int err;
|
|
u32 cell[3];
|
|
|
|
err = fdtdec_get_int_array(blob, node, "interrupts", cell,
|
|
ARRAY_SIZE(cell));
|
|
if (err)
|
|
return PERIPH_ID_NONE;
|
|
|
|
/* check for invalid peripheral id */
|
|
if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
|
|
return cell[1];
|
|
|
|
debug(" invalid peripheral id\n");
|
|
return PERIPH_ID_NONE;
|
|
}
|
|
|
|
int pinmux_decode_periph_id(const void *blob, int node)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
return exynos5_pinmux_decode_periph_id(blob, node);
|
|
else
|
|
return PERIPH_ID_NONE;
|
|
}
|
|
#endif
|