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https://github.com/AsahiLinux/u-boot
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89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
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*
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* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
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*
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* Based on drivers/usb/musb/davinci.h
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*
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* Copyright (C) 2009 Texas Instruments Incorporated
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*/
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#ifndef __DA8XX_MUSB_H__
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#define __DA8XX_MUSB_H__
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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/* Base address of da8xx usb0 wrapper */
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#define DA8XX_USB_OTG_BASE 0x01E00000
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/* Base address of da8xx musb core */
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#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
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/* Timeout for DA8xx usb module */
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#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
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/*
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* DA8xx platform USB wrapper register overlay.
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*/
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struct da8xx_usb_regs {
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dv_reg revision;
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dv_reg control;
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dv_reg status;
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dv_reg emulation;
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dv_reg mode;
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dv_reg autoreq;
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dv_reg srpfixtime;
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dv_reg teardown;
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dv_reg intsrc;
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dv_reg intsrc_set;
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dv_reg intsrc_clr;
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dv_reg intmsk;
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dv_reg intmsk_set;
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dv_reg intmsk_clr;
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dv_reg intsrcmsk;
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dv_reg eoi;
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dv_reg intvector;
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dv_reg grndis_size[4];
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};
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#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
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/* DA8XX interrupt bits definitions */
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#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
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#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
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#define DA8XX_USB_TXINT_SHIFT 0
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#define DA8XX_USB_RXINT_SHIFT 8
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#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
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#define DA8XX_USB_TXINT_MASK \
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(DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
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#define DA8XX_USB_RXINT_MASK \
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(DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
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/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
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#define CFGCHIP2_PHYCLKGD (1 << 17)
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#define CFGCHIP2_VBUSSENSE (1 << 16)
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#define CFGCHIP2_RESET (1 << 15)
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#define CFGCHIP2_OTGMODE (3 << 13)
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#define CFGCHIP2_NO_OVERRIDE (0 << 13)
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#define CFGCHIP2_FORCE_HOST (1 << 13)
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#define CFGCHIP2_FORCE_DEVICE (2 << 13)
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#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
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#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
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#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
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#define CFGCHIP2_PHYPWRDN (1 << 10)
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#define CFGCHIP2_OTGPWRDN (1 << 9)
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#define CFGCHIP2_DATPOL (1 << 8)
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#define CFGCHIP2_USB1SUSPENDM (1 << 7)
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#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
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#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
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#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
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#define CFGCHIP2_REFFREQ (0xf << 0)
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#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
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#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
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#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
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#define DA8XX_USB_VBUS_GPIO (1 << 15)
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#endif /* __DA8XX_MUSB_H__ */
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