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https://github.com/AsahiLinux/u-boot
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41a9fab8da
Since commit3d296365e4("mmc: sdhci: Add support for sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc field. Move the mmc field initialization before sdhci_setup_cfg() call to avoid crash on mmc pointer dereference. Fixes:3d296365e4("mmc: sdhci: Add support for sdhci-caps-mask") Cc: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell SD Host Controller Interface
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <linux/mbus.h>
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#define MVSDH_NAME "mv_sdh"
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#define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
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#define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
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static void sdhci_mvebu_mbus_config(void __iomem *base)
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{
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const struct mbus_dram_target_info *dram;
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int i;
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dram = mvebu_mbus_dram_info();
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for (i = 0; i < 4; i++) {
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writel(0, base + SDHCI_WINDOW_CTRL(i));
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writel(0, base + SDHCI_WINDOW_BASE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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/* Write size, attributes and target id to control register */
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writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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base + SDHCI_WINDOW_CTRL(i));
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/* Write base address to base register */
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writel(cs->base, base + SDHCI_WINDOW_BASE(i));
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}
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}
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#ifndef CONFIG_DM_MMC
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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static struct sdhci_ops mv_ops;
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#if defined(CONFIG_SHEEVA_88SV331xV5)
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#define SD_CE_ATA_2 0xEA
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#define MMC_CARD 0x1000
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#define MMC_WIDTH 0x0100
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static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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struct mmc *mmc = host->mmc;
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u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
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if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
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if (mmc->bus_width == 8)
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writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
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else
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writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
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}
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writeb(val, host->ioaddr + reg);
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}
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#else
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#define mv_sdhci_writeb NULL
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#endif /* CONFIG_SHEEVA_88SV331xV5 */
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#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
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int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
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{
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struct sdhci_host *host = NULL;
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host = calloc(1, sizeof(*host));
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if (!host) {
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printf("sdh_host malloc fail!\n");
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return -ENOMEM;
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}
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host->name = MVSDH_NAME;
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host->ioaddr = (void *)regbase;
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host->quirks = quirks;
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host->max_clk = max_clk;
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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memset(&mv_ops, 0, sizeof(struct sdhci_ops));
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mv_ops.write_b = mv_sdhci_writeb;
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host->ops = &mv_ops;
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#endif
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if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
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/* Configure SDHCI MBUS mbus bridge windows */
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sdhci_mvebu_mbus_config((void __iomem *)regbase);
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}
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return add_sdhci(host, 0, min_clk);
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}
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#else
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DECLARE_GLOBAL_DATA_PTR;
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struct mv_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int mv_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct mv_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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int ret;
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host->name = MVSDH_NAME;
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host->ioaddr = (void *)devfdt_get_addr(dev);
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host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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host->mmc->priv = host;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
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if (ret)
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return ret;
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if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
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/* Configure SDHCI MBUS mbus bridge windows */
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sdhci_mvebu_mbus_config(host->ioaddr);
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}
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upriv->mmc = host->mmc;
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return sdhci_probe(dev);
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}
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static int mv_sdhci_bind(struct udevice *dev)
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{
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struct mv_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id mv_sdhci_ids[] = {
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{ .compatible = "marvell,armada-380-sdhci" },
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{ }
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};
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U_BOOT_DRIVER(mv_sdhci_drv) = {
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.name = MVSDH_NAME,
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.id = UCLASS_MMC,
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.of_match = mv_sdhci_ids,
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.bind = mv_sdhci_bind,
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.probe = mv_sdhci_probe,
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.ops = &sdhci_ops,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct mv_sdhci_plat),
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};
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#endif /* CONFIG_DM_MMC */
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