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https://github.com/AsahiLinux/u-boot
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ed86e4fba1
This patch adds basic support for MediaTek MT7981 SoC. This include the file that will initialize the SoC after boot and its device tree. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
295 lines
7.9 KiB
Text
295 lines
7.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7981-clk.h>
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#include <dt-bindings/reset/mt7629-reset.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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/ {
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compatible = "mediatek,mt7981";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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mediatek,hwver = <&hwver>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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mediatek,hwver = <&hwver>;
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};
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};
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gpt_clk: gpt_dummy20m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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hwver: hwver {
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compatible = "mediatek,hwver", "syscon";
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reg = <0x8000000 0x1000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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clock-frequency = <13000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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arm,cpu-registers-not-fw-configured;
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};
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timer0: timer@10008000 {
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compatible = "mediatek,mt7986-timer";
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reg = <0x10008000 0x1000>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gpt_clk>;
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clock-names = "gpt-clk";
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u-boot,dm-pre-reloc;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt";
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reg = <0x1001c000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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status = "disabled";
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0x0c000000 0x40000>, /* GICD */
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<0x0c080000 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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fixed_plls: apmixedsys@1001e000 {
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compatible = "mediatek,mt7981-fixed-plls";
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reg = <0x1001e000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7981-topckgen";
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reg = <0x1001b000 0x1000>;
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clock-parent = <&fixed_plls>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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infracfg_ao: infracfg_ao@10001000 {
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compatible = "mediatek,mt7981-infracfg_ao";
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reg = <0x10001000 0x80>;
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clock-parent = <&infracfg>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7981-infracfg";
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reg = <0x10001000 0x30>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: pinctrl@11d00000 {
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compatible = "mediatek,mt7981-pinctrl";
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reg = <0x11d00000 0x1000>,
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<0x11c00000 0x1000>,
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<0x11c10000 0x1000>,
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<0x11d20000 0x1000>,
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<0x11e00000 0x1000>,
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<0x11e20000 0x1000>,
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<0x11f00000 0x1000>,
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<0x11f10000 0x1000>,
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<0x1000b000 0x1000>;
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reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
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"iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
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"iocfg_tm_base", "iocfg_tl_base", "eint";
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0x10048000 0x1000>;
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#clock-cells = <1>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_PWM>,
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<&infracfg_ao CK_INFRA_PWM_BSEL>,
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<&infracfg_ao CK_INFRA_PWM1_CK>,
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<&infracfg_ao CK_INFRA_PWM2_CK>,
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/* FIXME */
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<&infracfg_ao CK_INFRA_PWM2_CK>;
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assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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mediatek,force-highspeed;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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uart1: serial@11003000 {
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compatible = "mediatek,hsuart";
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reg = <0x11003000 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART1_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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mediatek,force-highspeed;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,hsuart";
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reg = <0x11004000 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART2_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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mediatek,force-highspeed;
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status = "disabled";
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};
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snand: snand@11005000 {
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compatible = "mediatek,mt7986-snand";
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reg = <0x11005000 0x1000>,
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<0x11006000 0x1000>;
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reg-names = "nfi", "ecc";
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clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
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<&infracfg_ao CK_INFRA_NFI1_CK>,
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<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
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clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
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assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
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<&topckgen CK_TOP_NFI1X_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
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<&topckgen CK_TOP_CB_M_D8>;
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status = "disabled";
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};
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ethsys: syscon@15000000 {
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compatible = "mediatek,mt7981-ethsys", "syscon";
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reg = <0x15000000 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7981-eth", "syscon";
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reg = <0x15100000 0x20000>;
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resets = <ðsys ETHSYS_FE_RST>;
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reset-names = "fe";
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7986-sgmiisys", "syscon";
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reg = <0x10060000 0x1000>;
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pn_swap;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7986-sgmiisys", "syscon";
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reg = <0x10070000 0x1000>;
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#clock-cells = <1>;
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,ipm-spi";
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reg = <0x1100a000 0x100>;
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clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
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<&topckgen CK_TOP_SPI_SEL>;
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assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
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<&infracfg CK_INFRA_SPI0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
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<&topckgen CK_INFRA_ISPI0>;
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clock-names = "sel-clk", "spi-clk";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi1: spi@1100b000 {
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compatible = "mediatek,ipm-spi";
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reg = <0x1100b000 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi2: spi@11009000 {
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compatible = "mediatek,ipm-spi";
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reg = <0x11009000 0x100>;
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clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
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<&topckgen CK_TOP_SPI_SEL>;
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assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
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<&infracfg CK_INFRA_SPI0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
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<&topckgen CK_INFRA_ISPI0>;
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clock-names = "sel-clk", "spi-clk";
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7981-mmc";
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reg = <0x11230000 0x1000>,
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<0x11C20000 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CK_TOP_EMMC_400M>,
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<&topckgen CK_TOP_EMMC_208M>,
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<&infracfg_ao CK_INFRA_MSDC_CK>;
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assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
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<&topckgen CK_TOP_EMMC_208M_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
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<&topckgen CK_TOP_CB_M_D2>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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};
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