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https://github.com/AsahiLinux/u-boot
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23d24df34c
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
85 lines
2 KiB
C
85 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Google Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pwm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pwm.h>
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struct tegra_pwm_priv {
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struct pwm_ctlr *regs;
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};
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static int tegra_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct tegra_pwm_priv *priv = dev_get_priv(dev);
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struct pwm_ctlr *regs = priv->regs;
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const u32 pwm_max_freq = dev_get_driver_data(dev);
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uint pulse_width;
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u32 reg;
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if (channel >= 4)
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return -EINVAL;
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debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
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clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq);
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pulse_width = duty_ns * 255 / period_ns;
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reg = pulse_width << PWM_WIDTH_SHIFT;
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reg |= 1 << PWM_DIVIDER_SHIFT;
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reg |= PWM_ENABLE_MASK;
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writel(reg, ®s[channel].control);
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debug("%s: pulse_width=%u\n", __func__, pulse_width);
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return 0;
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}
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static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct tegra_pwm_priv *priv = dev_get_priv(dev);
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struct pwm_ctlr *regs = priv->regs;
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if (channel >= 4)
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return -EINVAL;
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debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
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clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK,
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enable ? PWM_ENABLE_MASK : 0);
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return 0;
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}
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static int tegra_pwm_of_to_plat(struct udevice *dev)
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{
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struct tegra_pwm_priv *priv = dev_get_priv(dev);
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priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
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return 0;
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}
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static const struct pwm_ops tegra_pwm_ops = {
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.set_config = tegra_pwm_set_config,
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.set_enable = tegra_pwm_set_enable,
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};
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static const struct udevice_id tegra_pwm_ids[] = {
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{ .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 },
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{ .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 },
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{ }
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};
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U_BOOT_DRIVER(tegra_pwm) = {
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.name = "tegra_pwm",
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.id = UCLASS_PWM,
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.of_match = tegra_pwm_ids,
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.ops = &tegra_pwm_ops,
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.of_to_plat = tegra_pwm_of_to_plat,
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.priv_auto = sizeof(struct tegra_pwm_priv),
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};
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