mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 06:42:56 +00:00
09f3ca3dd5
We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
334 lines
9.1 KiB
C
334 lines
9.1 KiB
C
/*
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* (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
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* wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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#define CONFIG_V38B 1 /* ...on V38B board */
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TEXT_BASE 0xFF000000
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
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#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
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#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
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#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
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#define CONFIG_NETCONSOLE 1
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#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* DDR
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*/
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#define SDRAM_DDR 1 /* is DDR */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x704f0f00
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#define SDRAM_CONFIG1 0x73722930
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#define SDRAM_CONFIG2 0x47770000
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#define SDRAM_TAPDELAY 0x10000000
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/*
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* PCI - no suport
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*/
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#undef CONFIG_PCI
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/*
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* Partitions
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*/
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#define CONFIG_MAC_PARTITION 1
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#define CONFIG_DOS_PARTITION 1
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/*
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* USB
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*/
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_FAT
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Boot low with 16 MB Flash
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*/
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#define CONFIG_SYS_LOWBOOT 1
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#define CONFIG_SYS_LOWBOOT16 1
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootcmd=run net_nfs\0" \
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"bootdelay=3\0" \
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"baudrate=115200\0" \
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"preboot=echo;echo Type \"run flash_nfs\" to mount root " \
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"filesystem over NFS; echo\0" \
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"netdev=eth0\0" \
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"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):" \
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"$(netmask):$(hostname):$(netdev):off panic=1\0" \
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"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
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"flash_self=run ramargs addip;bootm $(kernel_addr) " \
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"$(ramdisk_addr)\0" \
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"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath) wdt=off\0" \
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"hostname=v38b\0" \
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"ethact=FEC\0" \
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"rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
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"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
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"cp.b 200000 ff000000 $(filesize);" \
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"prot on ff000000 ff03ffff\0" \
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"load=tftp 200000 $(u-boot)\0" \
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"netmask=255.255.0.0\0" \
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"ipaddr=192.168.160.18\0" \
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"serverip=192.168.1.1\0" \
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"bootfile=/tftpboot/v38b/uImage\0" \
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"u-boot=/tftpboot/v38b/u-boot.bin\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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/*
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* IPB Bus clocking configuration.
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*/
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#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
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/*
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* RTC configuration
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*/
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* Flash configuration - use CFI driver
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_MII 1
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/*
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* GPIO configuration
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x00047801
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*
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* IDE/ATA (supports IDE harddisk)
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_RESET /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
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#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
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/*
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* Status LED
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*/
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#define CONFIG_STATUS_LED /* Status LED enabled */
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#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
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#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
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#ifndef __ASSEMBLY__
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typedef unsigned int led_id_t;
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#define __led_toggle(_msk) \
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do { \
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*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
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} while(0)
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#define __led_set(_msk, _st) \
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do { \
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if ((_st)) \
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*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
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else \
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*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
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} while(0)
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#define __led_init(_msk, st) \
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do { \
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*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
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} while(0)
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIG_H */
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