mirror of
https://github.com/AsahiLinux/u-boot
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79ed61e9f0
Make the code structure more general so that more socs can be added easily and also remove speed limitation restriction. Add the ls1012a sata support as well. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (with and without CONFIG_OF_LIVE on zynqmp zcu102) Reviewed-by: York Sun <york.sun@nxp.com>
175 lines
4 KiB
C
175 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 - 2016 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <asm/io.h>
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/* Vendor Specific Register Offsets */
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#define AHCI_VEND_PCFG 0xA4
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#define AHCI_VEND_PPCFG 0xA8
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#define AHCI_VEND_PP2C 0xAC
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#define AHCI_VEND_PP3C 0xB0
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#define AHCI_VEND_PP4C 0xB4
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#define AHCI_VEND_PP5C 0xB8
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#define AHCI_VEND_AXICC 0xBc
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#define AHCI_VEND_PAXIC 0xC0
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#define AHCI_VEND_PTC 0xC8
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/* Vendor Specific Register bit definitions */
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#define PAXIC_ADBW_BW64 0x1
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#define PAXIC_MAWIDD (1 << 8)
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#define PAXIC_MARIDD (1 << 16)
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#define PAXIC_OTL (0x4 << 20)
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#define PCFG_TPSS_VAL (0x32 << 16)
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#define PCFG_TPRS_VAL (0x2 << 12)
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#define PCFG_PAD_VAL 0x2
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#define PPCFG_TTA 0x1FFFE
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#define PPCFG_PSSO_EN (1 << 28)
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#define PPCFG_PSS_EN (1 << 29)
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#define PPCFG_ESDF_EN (1 << 31)
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#define PP2C_CIBGMN 0x0F
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#define PP2C_CIBGMX (0x25 << 8)
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#define PP2C_CIBGN (0x18 << 16)
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#define PP2C_CINMP (0x29 << 24)
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#define PP3C_CWBGMN 0x04
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#define PP3C_CWBGMX (0x0B << 8)
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#define PP3C_CWBGN (0x08 << 16)
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#define PP3C_CWNMP (0x0F << 24)
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#define PP4C_BMX 0x0a
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#define PP4C_BNM (0x08 << 8)
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#define PP4C_SFD (0x4a << 16)
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#define PP4C_PTST (0x06 << 24)
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#define PP5C_RIT 0x60216
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#define PP5C_RCT (0x7f0 << 20)
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#define PTC_RX_WM_VAL 0x40
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#define PTC_RSVD (1 << 27)
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#define PORT0_BASE 0x100
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#define PORT1_BASE 0x180
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/* Port Control Register Bit Definitions */
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#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
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#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
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#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
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#define PORT_SCTL_IPM (0x3 << 8)
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#define PORT_BASE 0x100
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#define PORT_OFFSET 0x80
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#define NR_PORTS 2
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#define DRV_NAME "ahci-ceva"
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#define CEVA_FLAG_BROKEN_GEN2 1
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/* flag bit definition */
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#define FLAG_COHERENT 1
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/* register config value */
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#define CEVA_PHY1_CFG 0xa003fffe
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#define CEVA_PHY2_CFG 0x28184d1f
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#define CEVA_PHY3_CFG 0x0e081509
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#define CEVA_TRANS_CFG 0x08000029
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#define CEVA_AXICC_CFG 0x3fffffff
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/* ecc addr-val pair */
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#define ECC_DIS_ADDR_CH2 0x80000000
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#define ECC_DIS_VAL_CH2 0x20140520
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enum ceva_soc {
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CEVA_1V84,
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CEVA_LS1012A,
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};
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struct ceva_sata_priv {
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ulong base;
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enum ceva_soc soc;
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ulong flag;
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};
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static int ceva_init_sata(struct ceva_sata_priv *priv)
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{
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ulong base = priv->base;
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ulong tmp;
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switch (priv->soc) {
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case CEVA_1V84:
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tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
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writel(tmp, base + AHCI_VEND_PAXIC);
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tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
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writel(tmp, base + AHCI_VEND_PCFG);
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tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
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writel(tmp, base + AHCI_VEND_PPCFG);
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tmp = PTC_RX_WM_VAL | PTC_RSVD;
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writel(tmp, base + AHCI_VEND_PTC);
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break;
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case CEVA_LS1012A:
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writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
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writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
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writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
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if (priv->flag & FLAG_COHERENT)
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writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
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break;
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}
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return 0;
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}
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static int sata_ceva_bind(struct udevice *dev)
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{
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struct udevice *scsi_dev;
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return ahci_bind_scsi(dev, &scsi_dev);
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}
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static int sata_ceva_probe(struct udevice *dev)
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{
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struct ceva_sata_priv *priv = dev_get_priv(dev);
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ceva_init_sata(priv);
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return ahci_probe_scsi(dev, priv->base);
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}
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static const struct udevice_id sata_ceva_ids[] = {
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{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
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{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
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{ }
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};
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static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
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{
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struct ceva_sata_priv *priv = dev_get_priv(dev);
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if (dev_read_bool(dev, "dma-coherent"))
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priv->flag |= FLAG_COHERENT;
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->soc = dev_get_driver_data(dev);
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return 0;
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}
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U_BOOT_DRIVER(ceva_host_blk) = {
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.name = "ceva_sata",
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.id = UCLASS_AHCI,
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.of_match = sata_ceva_ids,
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.bind = sata_ceva_bind,
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.ops = &scsi_ops,
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.priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
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.probe = sata_ceva_probe,
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.ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
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};
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