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81ea00838c
When an operating system started via bootefi tries to reset or power off this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system the actual reset relies on PSCI. Depending on whether the PSCI firmware resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC or an SMC command has to be issued. The current implementation always uses SMC. This results in crashes on systems where the PSCI firmware is implemented in the hypervisor, e.g. qemu-arm64_defconfig. The logic to decide which call is needed based on the device tree is already implemented in the PSCI firmware driver. During the EFI runtime the device driver model is not available. But we can minimize code duplication by merging the EFI runtime reset and poweroff code with the PSCI firmware driver. As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff and reset_misc routines let's move them into the same code module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
45 lines
1.1 KiB
ArmAsm
45 lines
1.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015, Linaro Limited
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*/
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#include <linux/linkage.h>
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#include <linux/arm-smccc.h>
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#include <generated/asm-offsets.h>
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.section .text.efi_runtime
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.macro SMCCC instr
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.cfi_startproc
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\instr #0
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ldr x4, [sp]
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stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
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stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
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ldr x4, [sp, #8]
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cbz x4, 1f /* no quirk structure */
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ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
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cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
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b.ne 1f
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str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
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1: ret
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.cfi_endproc
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.endm
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/*
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* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
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* unsigned long a3, unsigned long a4, unsigned long a5,
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
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* struct arm_smccc_quirk *quirk)
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*/
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ENTRY(__arm_smccc_smc)
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SMCCC smc
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ENDPROC(__arm_smccc_smc)
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/*
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* void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
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* unsigned long a3, unsigned long a4, unsigned long a5,
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
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* struct arm_smccc_quirk *quirk)
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*/
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ENTRY(__arm_smccc_hvc)
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SMCCC hvc
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ENDPROC(__arm_smccc_hvc)
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