mirror of
https://github.com/AsahiLinux/u-boot
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e9ccb2f526
Add core architecture code to support the px30 soc. This includes a separate tpl board file due to very limited sram size as well as a non-dm sdram driver, as this also has to fit into the tiny sram. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/sdram_px30.h>
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CUR_VALUE0 0x08
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#define TIMER_CUR_VALUE1 0x0c
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0 << 1)
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#define TIMER_RMODE (1 << 1)
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void secure_timer_init(void)
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{
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1);
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writel(TIMER_EN | TIMER_FMODE,
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CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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printascii("U-Boot TPL board init\n");
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#endif
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secure_timer_init();
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ret = sdram_init();
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if (ret)
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printascii("sdram_init failed\n");
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/* return to maskrom */
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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}
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