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https://github.com/AsahiLinux/u-boot
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e82024def6
MIO34 is connected to POWER_KILL signal. When MIO configuration is done in psu_init() and this pin is assigned to PMU but PMU configuration is not loaded yet. PMU gpio output is high that means board is powered off immediately. The patch is fixing this sequence that MIO34 stays assing to ps gpio IP. PMU config is loaded in SPL and then pin assigned to PMU through psu_post_config_data(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
88 lines
1.6 KiB
C
88 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/psu_init_gpl.h>
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#define PSU_MASK_POLL_TIME 1100000
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int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value)
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{
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int i = 0;
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while ((__raw_readl(add) & mask) != value) {
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if (i == PSU_MASK_POLL_TIME)
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return 0;
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i++;
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}
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return 1;
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}
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__weak int mask_poll(u32 add, u32 mask)
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{
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int i = 0;
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unsigned long addr = add;
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while (!(__raw_readl(addr) & mask)) {
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if (i == PSU_MASK_POLL_TIME)
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return 0;
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i++;
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}
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return 1;
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}
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__weak u32 mask_read(u32 add, u32 mask)
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{
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unsigned long addr = add;
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return __raw_readl(addr) & mask;
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}
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__weak void mask_delay(u32 delay)
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{
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udelay(delay);
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}
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__weak void psu_mask_write(unsigned long offset, unsigned long mask,
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unsigned long val)
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{
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unsigned long regval = 0;
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regval = readl(offset);
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regval &= ~(mask);
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regval |= (val & mask);
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writel(regval, offset);
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}
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__weak void prog_reg(unsigned long addr, unsigned long mask,
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unsigned long shift, unsigned long value)
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{
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int rdata = 0;
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rdata = readl(addr);
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rdata = rdata & (~mask);
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rdata = rdata | (value << shift);
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writel(rdata, addr);
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}
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__weak int psu_init(void)
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{
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/*
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* This function is overridden by the one in
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* board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
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*/
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return -1;
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}
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__weak unsigned long psu_post_config_data(void)
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{
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/*
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* This function is overridden by the one in
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* board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
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*/
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return 0;
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}
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